View MAX98088_4993953.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-5335; Rev 0; 6/10
TION KIT EVALUA BLE ILA AVA
Stereo Audio Codec with FLEXSOUND Technology
Features
S S S S S S S S S 5.6mW Power Comsumption (DAC to HP at 97dB DR) 101dB DR Stereo DAC (8kHz < fS < 96kHz) 93dB DR Stereo ADC (8kHz < fS < 96kHz) Stereo Low EMI Class D Amplifiers 950mW/Channel (8I, VSPKVDD_ = 4.2V) Efficient Class H Headphone Amplifier Differential Receiver Amplifier/Stereo Line Outputs 2 Stereo Single-Ended/Mono Differential Line Inputs 3 Differential Microphone Inputs FLEXSOUND Technology 5-Band Parametric EQ Automatic Level Control (ALC) Excursion Limiter Speaker Power Limiter Speaker Distortion Limiter Microphone Automatic Gain Control and Noise Gate Dual I2S/PCM/TDM Digital Audio Interfaces Asynchronous Digital Mixing Supports Master Clock Frequencies from 10MHz to 60MHz RF Immune Analog Inputs and Outputs Extensive Click-and-Pop Reduction Circuitry Available in 63-Bump WLP Package (3.80mm x 3.30mm, 0.4mm Pitch)
General Description
The MAX98088 is a full-featured audio codec whose high performance and low power consumption make it ideal for portable applications. Class D speaker amplifiers provide efficient amplification for two speakers. Low radiated emissions enable completely filterless operation. Integrated bypass switches optionally connect an external amplifier to the transducer when the Class D amplifiers are disabled. The IC features a stereo Class H headphone amplifier that utilizes a dual-mode charge pump to maximize efficiency while outputting a ground referenced signal that does not require output coupling capacitors. The IC also features a mono differential amplifier that can also be configured as a stereo line output. Three differential analog microphone inputs are available as well as support for two PDM digital microphones. Integrated switches allow microphone signals to be routed out to external devices. Two flexible single-ended or differential line inputs may be connected to an FM radio or other sources. Integrated FLEXSOUNDK technology improves loudspeaker performance by optimizing the signal level and frequency response while limiting the maximum distortion and power at the output to prevent speaker damage. Automatic gain control (AGC) and a noise gate optimize the signal level of microphone input signals to make best use of the ADC dynamic range. The device is fully specified over the -40NC to +85NC extended temperature range.
FLEXSOUND is a trademark of Maxim Integrated Products, Inc.
MAX98088
S S S S S S
Ordering Information
PART MAX98088EWY+ TEMP RANGE -40NC to +85NC PIN-PACKAGE 63 WLP
+Denotes lead(Pb)-free/RoHS-compliant package.
Simplified Block Diagram
I2C I2S/PCM I2S/PCM RECEIVER/LINEOUT AMPS CONTROL DIGITAL MICROPHONE INPUT DIGITAL AUDIO INTERFACE DIGITAL AUDIO INTERFACE
FLEXSOUND TECHNOLOGY ADC * 5-BAND PARAMETRIC EQ * AUTOMATIC LEVEL CONTROL * LOUDSPEAKER PROCESSING * EXCURSION LIMITER * THD LIMITER * POWER LIMITER * MICROPHONE PROCESSING * AUTOMATIC GAIN CONTROL * NOISE GATE * ASYNCHRONOUS DIGITAL MIXING SPEAKER AMP
DAC
MIX LINEIN A1 ADC LINEIN A2
SPEAKER AMP MIX DAC HEADPHONE AMP
+
LINEIN B1
MAX98088
LINEIN B2
+
HEADPHONE AMP
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table of ConTenTs
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Digital Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Audio Interface Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Digital Microphone Timing Characterstics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C Timing Characterstics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Microphone to ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Line to ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Line In Pin Direct to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Digital Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Analog Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DAC to Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Line to Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DAC to Line Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Line to Line Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DAC to Speaker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Line to Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DAC to Headphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Lint to Headphone. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Speaker Bypass Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I2C Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Microphone Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Line Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ADC Input Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table of ConTenTs (continued)
Record Path Signal Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Microphone AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Noise Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ADC Record Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Sidetone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Digital Audio Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Clock Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Sample Rate Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Passband Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Playback Path Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Automatic Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Parametric Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Playback Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 DAC Input Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Receiver Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Receiver Output Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Receiver Output Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Speaker Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Speaker Output Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Speaker Amplifier Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Excursion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Speaker Output Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Power Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Headphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 DirectDrive Headphone Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Class H Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Headphone Output Mixers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Headphone Output Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Output Bypass Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Click-and-Pop Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Jack Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Jack Detection and Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table of ConTenTs (continued)
Battery Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Device Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Early STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Device Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Typical Operating Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Filterless Class D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 RF Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Startup/Shutdown Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Optional Ferrite Bead Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Charge-Pump Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Charge-Pump Flying Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Charge-Pump Holding Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Recommended PCB Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Supply Bypassing, Layout, and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 WLP Applications Information (MAX98088) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4
F4 D1 G4 DVDD AVDD G5 BCLKS1 LRCLKS2 PORT S2 SDOUTS2 SDINS2 DVDDS2 PORT S1 LRCLKS1 SDOUTS1 SDINS1 DVDDS1 BCLKS2 D4 D2 E4 E1 F2 F3 G1 G3 G2 MCLK
F5
E5
E2
SDA SCL IRQ
I2C
SEL1 BCLK1 SDIN1 BCLK2 LRCLK1 LRCLK2 SDOUT1 SDOUT2 SDIN2
SEL2
MAX98088
REF BIAS REG G6 F6
E6 JACKSNS DAI1 MAS1 BIT CLOCK FRAME CLOCK DATA OUTPUT DATA INPUT BIT CLOCK FRAME CLOCK DATA OUTPUT DATA INPUT MAS1 HIZOFF1 MAS2 MAS2 HIZOFF2 DAI2
JACK DETECTION
JDETEN
F7 MICBIAS MUX LBEN2
REG
LBEN1
RECVOLL: +8dB TO -62dB MIX 0dB RECLEN
MBEN
+
LTEN1 MIXRECL DVST: 0dB TO -60dB DV1G: 0/6/12/18dB
RECP/ LOUTL/ RXINP
A6
CLOCK CONTROL SIDETONE MIX DSTS MULTI BAND ALC DVEQ1: 0dB TO -15dB NOISE GATE EQ1EN EXCURSION LIMITER MIX MIXDAL DACL DALEN EQ2EN DVEQ2: 0dB TO -15dB MIXRECR MIX
RECVOLR: +8dB TO -62dB 0dB LINEMODE
RECBYP
MIC1P/ E8 DIGMICDATA
+
FLEXSOUNDTM TECHNOLOGY
RECP/ LOUTR/ RXINP RECREN SPVOLL: +8dB TO -62dB
B6
PGAM1: +20dB TO 0dB
MIC1N/ F8 DIGMICCLK
SPKBYP
SPKLVDD SPKLP MIX +6dB SPLEN MIXSPL SPKLGND POWER/ DISTORTION LIMITER SPKRVDD SPKRP MIX SPVOLR: +8dB TO -62dB MIXSPR +6dB SPREN SPKRGND SPKRN SPKLN
A3, B3 A4, B4 A5, B5 C4, C5 C3, D3 C1, C2 A1, B1 A2, B2
EXTMIC 5-BAND PARAMETRIC EQ 5-BAND PARAMETRIC EQ
MIC2BYP MODE1 AVFLT ADLEN MIX DV2: 0dB TO -15dB DCB2 ADCL AUDIO/ FILTERS AUDIO/ VOICE FILTERS
PA1EN: 0/20/30dB
AUTOMATIC GAIN CONTROL
G9 MIC2P
PGAM2: +20dB TO 0dB
G8 MIC2N
EXTMIC
INABYP MIXADL SRMIX_ MODE SAMPLE RATE CONVERTER
PA2EN: 0/20/30dB
AVLG: 0/6/ 12/18dB AVL:0dB TO -15dB
AVRG: 0/6/ 12/18dB AVR:0dB TO -15dB
PGAINA: +20dB TO -6dB INADIFF ADCR ADREN MIXADR DV1: 0dB TO -15dB
F9 INA1/EXTMICP
MIX
AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR DAREN
E9 INA2/EXTMICN
+
PGAINA: +20dB TO -6dB
MIX
MIXHPL_ PATH SEL
HPVOLL: +3dB TO -67dB HPLEN MIXHPL
HPL
C9
PGAINB: +20dB TO -6dB
HPSNS
C8
E7 INB1
INBDIFF MIX
MIXHPR_ PATH SEL
D8 INB2
+
PGAINB: +20dB TO -6dB
HPVOR: +3dB TO -67dB
HPR MIXHPR HPREN PVDD CHARGE PUMP HPVDD HPVSS C1N C1P B9 A8 B8 B7 HPGND
D9
A7 A9
Stereo Audio Codec with FLEXSOUND Technology
Functional Diagram
MAX98088
5
Stereo Audio Codec with FLEXSOUND Technology MAX98088
ABSOLUTE MAXIMUM RATINGS
(Voltages with respect to AGND.) DVDD, AVDD, HPVDD .........................................-0.3V to +2.2V SPKLVDD, SPKRVDD, DVDDS1, DVDDS2 ..........-0.3V to +6.0V DGND, HPGND, SPKLGND, SPKRGND ..............-0.1V to +0.1V HPVSS ............................... (HPGND - 2.2V) to (HPGND + 0.3V) C1N .................................... (HPVSS - 0.3V) to (HPGND + 0.3V) C1P .....................................(HPGND - 0.3V) to (HPVDD + 0.3V) REF, MICBIAS ................................. -0.3V to (SPKLVDD + 0.3V) MCLK, SDINS1, SDINS2, JACKSNS, SDA, SCL, IRQ .................................................-0.3V to +6.0V LRCLKS1, BCLKS1, SDOUTS1 ......... -0.3V to (DVDDS1 + 0.3V) LRCLKS2, BCLKS2, SDOUTS2 ......... -0.3V to (DVDDS2 + 0.3V) REG, INA1, INA2, INB1, INB2, MIC1P/DIGMICDATA, MIC1N/DIGMICCLK, MIC2P, MIC2N ...............-0.3V to +2.2V HPSNS ............................... (HPGND - 0.3V) to (HPGND + 0.3V) HPL, HPR ............................ (HPVSS - 0.3V) to (HPVDD + 0.3V) RECP, RECN ..............(SPKLGND - 0.3V) to (SPKLVDD + 0.3V) SPKLP, SPKLN ...........(SPKLGND - 0.3V) to (SPKLVDD + 0.3V) SPKRP, SPKRN .........(SPKRGND - 0.3V) to (SPKRVDD + 0.3V) Continuous Power Dissipation (TA = +70NC) 63-Bump WLP (derate 25.6mW/NC above +70NC)........2.05W Operating Temperature Range .......................... -40NC to +85NC Storage Temperature Range............................ -65NC to +150NC Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER POWER SUPPLY VSPKLVDD, VSPKRVDD Supply Voltage Range Guaranteed by PSRR VDVDD, VAVDD, VPVDD VDVDDS1, VDVDDS2 Analog Full-duplex 8kHz mono, Speaker receiver output Digital Total Supply Current (Notes 2 and 3) IVDD DAC playback 48kHz stereo, headphone outputs DAC playback 48kHz stereo, speaker outputs Shutdown Supply Current (Note 2) REF Voltage REG Voltage Shutdown to Full Operation SLEW = 0 SLEW = 1 Analog Speaker Digital Analog Speaker Digital Analog TA = +25NC Speaker Digital 2.8 1.65 1.65 4.5 1.6 1.3 1.9 0.001 2.47 3.6 6.41 2.49 0.2 0.01 1 2.5 0.79 30 17 1.8 5.5 2 3.6 8 2.3 2 3 0.0058 3.5 6.5 8.5 3.5 2 1 5 V V ms FA mA V SYMBOL CONDITIONS MIN TYP MAX UNITS
6
Stereo Audio Codec with FLEXSOUND Technology
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS fS = 8kHz, MODE = 0 (IIR voice), AVMICPRE_ = 0dB (Note 4) VIN = 0.1VP-P, fS = 8kHz, f = 1kHz THD+N AVMICPRE_ = 0dB, VIN = 1VP-P, f = 1kHz AVMICPRE_ = +30dB, VIN = 32mVP-P, f = 1kHz CMRR VIN = 100mVP-P, f = 217Hz VAVDD = 1.65V to 1.95V, input referred, MIC inputs floating Power-Supply Rejection Ratio f = 217Hz, VRIPPLE = 100mVP-P, AVADC = 0dB, input referred f = 1kHz, VRIPPLE = 100mVP-P, AVADC = 0dB, input referred f = 10kHz, VRIPPLE = 100mVP-P, AVADC = 0dB, input referred MODE = 0 (IIR voice) 8kHz 1kHz, 0dB input, highpass filter disabled measured from analog input to digital output MODE = 0 (IIR voice) 16kHz MODE = 1 (FIR audio) 8kHz MODE = 1 (FIR audio) 48kHz MICROPHONE PREAMP Full-Scale Input Preamplifier Gain AVMICPRE_ = 0dB PA1EN/PA2EN = 01 AVMICPRE_ (Note 5) PA1EN/PA2EN = 10 PA1EN/PA2EN = 11 PGA Gain MIC Input Resistance AVMICPGA_ (Note 5) RIN_MIC PGAM1/PGAM2 = 0x00 PGAM1/PGAM2 = 0x14 19.5 29.5 19 1.05 0 20 30 20 0 50 20.5 30.5 21 dB kI dB VP-P 50 MIN TYP MAX UNITS MICROPHONE TO ADC PATH Dynamic Range Total Harmonic Distortion + Noise Common-Mode Rejection Ratio DR 88 -77 -84 -70 62 62 62 dB 62 53 2.2 1.1 ms 4.5 0.76 dB dB dB
MAX98088
PSRR
Path Phase Delay
All gain settings, measured at MIC1P/ MIC1N/MIC2P/MIC2N
7
Stereo Audio Codec with FLEXSOUND Technology MAX98088
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER MICROPHONE BIAS MICBIAS Output Voltage Load Regulation Line Regulation Ripple Rejection VMICBIAS ILOAD = 1mA ILOAD = 1mA to 2mA VSPKLVDD = 2.8V to 5.5V f = 217Hz, VRIPPLE (SPKLVDD) = 100mVP-P f = 10kHz, VRIPPLE (SPKLVDD) = 100mVP-P A-weighted, f = 20Hz to 20kHz P-weighted, f = 20Hz to 4kHz f = 1kHz MICROPHONE BYPASS SWITCH On-Resistance Total Harmonic Distortion + Noise Off-Isolation Off-Leakage Current LINE INPUT TO ADC PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise Gain Error DR THD+N INA pin direct, fS = 48kHz, MODE = 1 (FIR audio) VIN = 1VP-P, f = 1kHz DC accuracy VAVDD = 1.65V to 1.95V, input referred, line inputs floating Power-Supply Rejection Ratio f = 217Hz, VRIPPLE = 100mVP-P, AVADC = 0dB, input referred f = 1kHz, VRIPPLE = 100mVP-P, AVADC = 0dB, input referred f = 10kHz, VRIPPLE = 100mVP-P, AVADC = 0dB, input referred 57 93 82 1 68 72 dB 70 60 74 dB dB % RON THD+N IMIC1_ = 100mA, INABYP = MIC2BYP = 1, VMIC2_ = VINA_ = 0V, AVDD, TA = +25NC VIN = 2VP-P, VCM = 0.9V, RL = 10kI, f = 1kHz, INABYP = MIC2BYP = 1 VIN = 2VP-P, VCM = 0.9V, RL = 10kI, f = 1kHz VMIC1_ = [0V, AVDD], VMIC2_/VINA_ = [AVDD, 0V] -1 5 -80 60 +1 30 I dB dB FA 2.15 2.2 0.5 110 92 83 3.9 2.1 50 2.25 4.5 V mV FV dB FVRMS nV/Hz SYMBOL CONDITIONS MIN TYP MAX UNITS
Noise Voltage
PSRR
8
Stereo Audio Codec with FLEXSOUND Technology
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER LINE INPUT PREAMP Full-Scale Input VIN AVPGAIN_ = 0dB AVPGAIN_ = -6dB PGAINA/PGAINB = 0x0 PGAINA/PGAINB = 0x1 Level Adjust Gain AVPGAIN_ TA = +25NC (Note 5) PGAINA/PGAINB = 0x2 PGAINA/PGAINB = 0x3 PGAINA/PGAINB = 0x4 PGAINA/PGAINB = 0x5, 0x6, 0x7 AVPGAIN_ = +20dB AVPGAIN_ = +14dB Input Resistance RIN AVPGAIN_ = +3dB AVPGAIN_ = 0dB AVPGAIN_ = -3dB AVPGAIN_ = -6dB Feedback Resistance ADC LEVEL CONTROL ADC Level Adjust Range ADC Level Step Size ADC Gain Adjust Range ADC Gain Adjust Step Size ADC DIGITAL FILTERS VOICE MODE IIR LOWPASS FILTER (MODE1 = 0) Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation (Note 6) fSLP f > fSLP 74 fPLP Ripple limit cutoff -3dB cutoff f < fPLP 0.441 x fs 0.449 x fs -0.1 +0.1 0.47 x fS Hz dB Hz dB AVADCGAIN AVLG/AVRG = 00 to 11 (Note 5) 0 6 AVADCLVL AVL/AVR = 0xF to 0x0 (Note 5) -12 1 18 +3 dB dB dB dB RIN_FB INAEXT/INBEXT = 1 TA = +25NC TA = TMIN to TMAX 18 16 7.5 -4 -7 14.5 19 13 2 1 1.4 20 14 3 0 -3 -6 21 20 20 10 20 20 20 22 24 kI 14 kI -2 -5 28 21 15 4 dB VP-P SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX98088
9
Stereo Audio Codec with FLEXSOUND Technology MAX98088
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS AVFLT = 0x1 (Elliptical tuned for fS = 16kHz + 217Hz notch) AVFLT = 0x2 (500Hz Butterworth tuned for fS = 16kHz) Passband Cutoff (-3dB from Peak) fAHPPB AVFLT = 0x3 (Elliptical tuned for fS = 8kHz + 217Hz notch) AVFLT = 0x4 (500Hz Butterworth tuned for fS = 8kHz) AVFLT = 0x5 (fS/240 Butterworth) AVFLT = 0x1 (Elliptical tuned for fS = 16kHz + 217Hz notch) AVFLT = 0x2 (500Hz Butterworth tuned for fS = 16kHz) Stopband Cutoff (-30dB from Peak) fAHPSB AVFLT = 0x3 (Elliptical tuned for fS = 8kHz + 217Hz notch) AVFLT = 0x4 (500Hz Butterworth tuned for fS = 8kHz) AVFLT = 0x5 (fS/240 Butterworth) DC Attenuation DCATTEN AVFLT 000 Ripple limit cutoff Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation (Note 6) fSLP f < fSLP 60 fPLP -3dB cutoff -6.02dB cutoff f < fPLP 0.43 x fS 0.48 x fS 0.5 x fS -0.1 +0.1 0.58 x fS dB Hz dB Hz 0.0139 x fS 0.0156 x fS 0.0279 x fS 0.0312 x fS 0.0018 x fS 90 dB Hz MIN TYP MAX 0.0161 x fS 0.0319 x fS 0.0321 x fS 0.0632 x fS 0.0043 x fS Hz UNITS VOICE MODE IIR HIGHPASS FILTER (MODE1 = 0)
STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1 = 0, LRCLK < 50kHz)
ADC STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1 = 1, LRCLK > 50kHz) Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation fSLP f < fSLP 60 fPLP Ripple limit cutoff -3dB cutoff f < fPLP 0.208 x fS 0.28 x fS -0.1 +0.1 0.417 x fS Hz dB Hz dB
10
Stereo Audio Codec with FLEXSOUND Technology
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER Passband Cutoff (-3dB from Peak) DC Attenuation SYMBOL CONDITIONS MIN TYP MAX 0.000125 x fS 90 50 400 2 123 0.078 10 -3 1 (Note 5) ANTH = 0x3 to 0xF, referred to 0dBFS (Note 5) DVST = 0x01 DVST = 0x1F 0 -64 0 -0.5 -60.5 2 1kHz, 0dB input, highpass filter disabled 8kHz 16kHz 2.2 1.1 20 -16 12 +18 UNITS ADC STEREO AUDIO MODE DC BLOCKING HIGHPASS FILTER (MODE1 = 1) fAHPPB DCAtten AVFLT 000 AVFLT 000 AGCHLD = 01 AGCHLD = 11 AGCATK = 00 AGCATK = 11 AGCRLS = 000 AGCRLS = 111 AGCTH = 0x0 to 0xF Hz dB
MAX98088
MICROPHONE AUTOMATIC GAIN CONTROL AGC Hold Duration AGC Attack Time AGC Release Time AGC Threshold Level AGC Threshold Step Size AGC Gain ADC NOISE GATE NG Threshold Level NG Attenuation Sidetone Gain Adjust Range Sidetone Gain Adjust Step Size Sidetone Path Phase Delay dB dB ms ms s dB dB dB
ADC-TO-DAC DIGITAL SIDETONE (MODE = 0) AVSTGA dB dB ms
ADC-TO-DAC DIGITAL LOOP-THROUGH PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise DAC LEVEL CONTROL DAC Attenuation Range DAC Attenuation Step Size DAC Gain Adjust Range DAC Gain Adjust Step Size AVDACGAIN DV1G = 00 to 11 (Note 5) 0 6 AVDACATTN DV1DV2 = 0xF to 0x0 (Note 5) -15 1 18 0 dB dB dB dB DR THD+N fS = 48kHz, MCLK = 12.288MHz, MODE = 1 (FIR audio), MIC to HP output, TA = +25NC f = 1kHz, fS = 48kHz, MCLK = 12.288MHz, MODE = 1 (FIR audio), MIC to HP output 83 93 81 dB dB
11
Stereo Audio Codec with FLEXSOUND Technology MAX98088
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER DAC DIGITAL FILTERS VOICE MODE IIR LOWPASS FILTER (MODE1 = 0) Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation (Note 6) fSLP f > fSLP 75 fPLP Ripple limit cutoff -3dB cutoff f < fPLP 0.448 x fS 0.451 x fS -0.1 +0.1 0.476 x fS Hz dB Hz dB SYMBOL CONDITIONS MIN TYP MAX UNITS
VOICE MODE IIR HIGHPASS FILTER (MODE1 = 0) DVFLT = 0x1 (Elliptical tuned for fS = 16kHz + 217Hz notch) DVFLT = 0x2 (500Hz Butterworth tuned for fS = 16kHz) Passband Cutoff (-3dB from Peak) fDHPPB DVFLT = 0x3 (Elliptical tuned for fS = 8kHz + 217Hz notch) DVFLT = 0x4 (500Hz Butterworth tuned for fS = 8kHz) DVFLT = 0x5 (fs/240 Butterworth) DVFLT = 0x1 (Elliptical tuned for fS = 16kHz + 217Hz notch) DVFLT = 0x2 (500Hz Butterworth tuned for fS = 16kHz) Stopband Cutoff (-30dB from Peak) fDHPSB DVFLT = 0x3 (Elliptical tuned for fS = 8kHz + 217Hz notch) DVFLT = 0x4 (500Hz Butterworth tuned for fS = 8kHz) DVFLT = 0x5 (fS/240 Butterworth) DC Attenuation DCATTEN DVFLT 000 Ripple limit cutoff Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation (Note 6) 12 fSLP f > fSLP 60 fPLP -3dB cutoff -6.02dB cutoff f < fPLP 0.43 x fS 0.47 x fS 0.5 x fS -0.1 +0.1 0.58 x fS Hz dB Hz dB 0.0139 x fS 0.0156 x fS 0.0279 x fS 0.0312 x fS 0.0021 x fS 85 dB Hz 0.0161 x fS 0.0312 x fS 0.0321 x fS 0.0625 x fS 0.0042 x fS Hz
STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1/DHF2 = 0, LRCLK < 50kHz)
Stereo Audio Codec with FLEXSOUND Technology
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL Ripple limit cutoff -3dB cutoff f < fPLP fSLP f < fSLP 60 CONDITIONS MIN 0.24 x fS 0.31 x fS -0.1 +0.1 0.477 x fS TYP MAX UNITS STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1/DHF2 = 1 for LRCLK > 50kHz) Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation (Note 6) Passband Cutoff (-3dB from Peak) DC Attenuation Dual Band Lowpass Corner Frequency Dual Band Highpass Corner Frequency Gain Range Low-Signal Threshold Release Time PARAMETRIC EQUALIZER Number of Bands Per Band Gain Range Preattenuator Gain Range Preattenuator Step Size DAC TO RECEIVER AMPLIFIER PATH Dynamic Range Total Harmonic Distortion + Noise Power-Supply Rejection Ratio DR THD+N fS = 48kHz, f = 1kHz (Note 4) f = 1kHz, POUT = 15mW, RREC = 32I VSPKLVDD = 2.8V to 5.5V PSRR f = 217Hz, VRIPPLE = 100mVP-P f = 1kHz, VRIPPLE = 100mVP-P f = 10kHz, VRIPPLE = 100mVP-P Click-and-Pop Level KCP Peak voltage, A-weighted, 32 samples per second, AVREC = 0dB Into shutdown Out of shutdown 64 96 70 75 -59 -59 -59 68 72 dBV dB 63 dB dB (Note 5) -12 -15 1 5 +12 0 Bands dB dB dB ALCTH = 111 to 001 ALCRLS = 101 ALCRLS = 000 fPLP Hz dB Hz dB
MAX98088
STEREO AUDIO MODE DC BLOCKING HIGHPASS FILTER fDHPPB DVFLT 000 (DAI1), DCB2 = 1 (DAI2) 90 0.000104 x fS Hz dB
DCATTEN DVFLT 000 (DAI1), DCB2 = 1 (DAI2)
AUTOMATIC LEVEL CONTROL ALCMB = 1 ALCMB = 1 0 -48 0.25 8 5 5 12 -12 kHz kHz dB dBFS s
13
Stereo Audio Codec with FLEXSOUND Technology MAX98088
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER Dynamic Range (Note 4) Total Harmonic Distortion + Noise Click-and-Pop Level RECEIVER AMPLIFIER Output Power Full-Scale Output Volume Control (Note 5) AVREC POUT RREC = 32I, f = 1kHz, THD = 1% (Note 7) RECVOL = 0x00 RECVOL = 0x1F +8dB to +6dB +6dB to +0dB Volume Control Step Size 0dB to -14dB -14dB to -38dB -38dB to -62dB Mute Attenuation Capacitive Drive Capability DAC TO LINE OUT AMPLIFIER PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise Dynamic Range (Note 4) Total Harmonic Distortion + Noise Full-Scale Output Mute Attenuation Output Offset Voltage Capacitive Drive Capability VOS DR THD+N fS = 48kHz, f = 1kHz f = 1kHz, RL = 1kI 83 96 78 72 dB dB f = 1kHz No sustained oscillations RREC = 32I RREC = J 83 1 -62 8 0.5 1 2 3 4 88 500 100 dB pF dB mW VRMS dB SYMBOL DR THD+N KCP Peak voltage, A-weighted, 32 samples per second, AVREC = 0dB Into shutdown Out of shutdown CONDITIONS Referenced to full-scale output level MIN TYP 94 64 -51 -49 MAX UNITS dB dB dBV LINE INPUT TO RECEIVER AMPLIFIER PATH
LINE INPUT TO LINE OUT AMPLIFIER PATH DR THD+N Referenced to full-scale output level f = 1kHz, RL = 10kI AVHP = 0dB, AVOUT = 0 dB (Note 7) f = 1kHz AVHP = -67dB No sustained oscillations, RL = 1kI 92 76 2 85 Q3.0 500 4 dB dB VP-P dB mV pF
14
Stereo Audio Codec with FLEXSOUND Technology
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER Total Harmonic Distortion + Noise Crosstalk Output Noise Click-and-Pop Level KCP Peak voltage, A-weighted, 32 samples per second, AVSPK_ = 0dB Into shutdown Out of shutdown SYMBOL CONDITIONS MIN TYP MAX UNITS DAC TO SPEAKER AMPLIFIER PATH THD+N f = 1kHz, POUT = 200mW, ZSPK = 8I + 68FH SPKL to SPKR and SPKR to SPKL, POUT = 640mW, f = 1kHz -68 -88 53 65 66 82 71 55 52 1323 914 700 514 2 SPVOLL/SPVOLR = 0x00 SPVOLL/SPVOLR = 0x1F -62 +8 0.5 1 2 3 4 86 Q0.5 Q3 dB mV dB VRMS dB mW dB dB FVRMS dBV
MAX98088
MIC INPUT TO SPEAKER AMPLIFIER PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise Click-and-Pop Level SPEAKER AMPLIFIER f = 1kHz, THD = 1%, ZSPK = 8I + 68FH (Note 7) AVSPK_ (Note 5) +8dB to +6dB +6dB to +0dB Volume Control Step Size 0dB to -14dB -14dB to -38dB -38dB to -64dB Mute Attenuation Output Offset Voltage VOS f = 1kHz AVSPK_ = -61dB, TA = +25NC VSPKLVDD = VSPKRVDD = 5.0V VSPKLVDD = VSPKRVDD = 4.2V VSPKLVDD = VSPKRVDD = 3.7V VSPKLVDD = VSPKRVDD = 3.2V DR THD+N KCP Referenced to full-scale output level, AVSPK_ = 0dB f = 1kHz, POUT = 200mW, RL = 8I + 68FH Peak voltage, A-weighted, 32 samples per second, AVSPK_ = 0dB Into shutdown Out of shutdown dB dB dBV
Output Power
POUT
Full-Scale Output Volume Control
15
Stereo Audio Codec with FLEXSOUND Technology MAX98088
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER EXCURSION LIMITER Upper Corner Frequency Range Lower Corner Frequency DHPUCF = 001 to 100 DHPLCF = 01 to 10 DHPUCF = 000 (fixed mode) Biquad Minimum Corner Frequency DHPUCF = 001 DHPUCF = 010 DHPUCF = 011 DHPUCF = 100 Threshold Voltage Release Time POWER LIMITER Attenuation Threshold Time Constant 1 Time Constant 2 Weighting Factor DISTORTION LIMITER Distortion Limit Release Time Constant THDCLP = 0x1 THDCLP = 0xF THDT1 = 000 THDT1 = 111 <1 24 0.76 6.2 % s tPWR1 tPWR2 kPWR ZSPK = 8I + 68FH, VSPKLVDD = VSPKRVDD = 5.5V, AVSPK_ = 8dB PWRT1 = 0x1 PWRT1 = 0xF PWRT2 = 0x1 to 0xF PWRT2 = 0xF PWRK = 000 to 111 12.5 PWRTH = 0x1 PWRTH = 0xF -64 0.08 1.23 0.5 8.7 0.5 8.7 100 dB W s min % ZSPK = 8I + 68FH, VSPKLVDD = VSPKRVDD = 5.5V, AVSPK_ = 8dB ALCRLS = 101 ALCRLS = 000 DHPTH = 000 DHPTH = 111 400 400 100 200 300 400 500 0.34 0.95 0.25 4 VP s Hz 1000 Hz Hz SYMBOL CONDITIONS MIN TYP MAX UNITS
16
Stereo Audio Codec with FLEXSOUND Technology
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS Master or slave mode Dynamic Range (Note 4) Total Harmonic Distortion + Noise Crosstalk DR fS = 48kHz Slave mode Low power mode THD+N f = 1kHz, POUT = 20mW RHP = 16I RHP = 32I 97 95 97 -84 -83 83 46 54 72 63 43 2.2 1.1 ms 4.5 0.76 1 1 KCP Peak voltage, A-weighted, 32 samples per second, AVHP_ = 0dB Into shutdown Out of shutdown -62 -63 5 % % dBV dB -64 dB dB MIN TYP 101 dB MAX UNITS DAC TO HEADPHONE AMPLIFIER PATH
MAX98088
HPL to HPR and HPR to HPL, POUT = 5mW, f = 1kHz, RHP = 32I VAVDD = VPVDD = 1.65V to 2.0V f = 217Hz, VRIPPLE = 200mVP-P, AVVOL = 0dB PSRR f = 1kHz, VRIPPLE = 200mVP-P, AVVOL = 0dB f = 10kHz, VRIPPLE = 200mVP-P, AVVOL = 0dB MODE = 0 (voice) 8kHz 1kHz, 0dB input, highpass filter disabled measured from digital input to analog output MODE = 0 (voice) 16kHz MODE = 1 (music) 8kHz MODE = 1 (music) 48kHz
Power-Supply Rejection Ratio
DAC Path Phase Delay
Gain Error Channel Gain Mismatch Click-and-Pop Level
LINE INPUT TO HEADPHONE AMPLIFIER PATH Total Harmonic Distortion + Noise Dynamic Range (Note 4) Click-and-Pop Level KCP Peak voltage, A-weighted, 32 samples per second, AVHP_ = 0dB Into shutdown Out of shutdown THD+N VIN = 1VP-P, f =1kHz, RL = 32I 81 92.5 -62 -63 dB dB dBV
17
Stereo Audio Codec with FLEXSOUND Technology MAX98088
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER HEADPHONE AMPLIFIER Output Power Positive Charge-Pump Output Voltage Negative Charge-Pump Output Voltage Output Voltage Threshold (Output Voltage at which the Charge Pump Switches Modes; VOUT Rising; Transition from Split to Invert Mode) Full-Scale Output Volume Control AVHP_ POUT HPVDD HPVSS f = 1kHz, THD = 1% VOUT = 0.2V, RL = J VOUT = 0.5V, RL = J VOUT = 0.2V, RL = J VOUT = 0.5V, RL = J RL = 32I RL = 16I 30 38 PVDD/2 PVDD -PVDD/2 -PVDD mW V V SYMBOL CONDITIONS MIN TYP MAX UNITS
VTH2
RL = J
QPVIN x 0.25
V
(Note 7) (Note 5) +3dB to +1dB +1dB to -5dB HPVOL_ = 0x00 HPVOL_ = 0x1F
1 -67 +3 0.5 1 2 3 4 100 TA = +25NC TA = TMIN to TMAX RHP = 32I RHP = J Q0.5 500 100 Q1 Q3
VRMS dB
Volume Control Step Size
-5dB to -19dB -19dB to -43dB -43dB to -67dB
dB
Mute Attenuation Output Offset Voltage Capacitive Drive Capability SPEAKER BYPASS SWITCH On-Resistance Total Harmonic Distortion + Noise Off-Isolation Off-Leakage Current RON THD+N VOS
f = 1kHz AVHP_ = -67dB No sustained oscillations
dB mV pF
ISPKL_ = 100mA, SPKBYP = 1, VRXIN_ = [0V, VSPKLVDD] VIN = 2VP-P, VCM = VSPKLVDD/2, RS = 10I ZSPK = 8I + 68FH, f = 1kHz, RS = 0I SPKBYP = 1 VIN = 2VP-P, VCM = VSPKLVDD/2, ZL = 8I + 68FH, f = 1kHz VRXIN_ = [0V, VSPKLVDD], VSPKL_ = [VSPKLVDD, 0V] -20
2.8 60 60 96 +20
I dB dB FA
18
Stereo Audio Codec with FLEXSOUND Technology MAX98088
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. Line out loads (RLOAD) connected from LOUTL and LOUTR to ground. RLOAD = RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS IRECP = 100mA, RECBYP = 1, VRECN = [0V, VSPKLVDD] VIN = 2VP-P, VCM = VSPKLVDD/2, ZL = 8I + 68FH, f = 1kHz, RECBYP = 1, RS = 0I VIN = 2VP-P, VCM = VSPKLVDD/2, ZL = 8I + 68FH, f = 1kHz VRECP = [0V, VSPKLVDD], VRECN = [VSPKLVDD, 0V] -15 MIN TYP MAX UNITS RECEIVER BYPASS SWITCH On-Resistance Total Harmonic Distortion + Noise Off-Isolation Off-Leakage Current JACK DETECTION SHDN = 1, JACKSNS rising JACKSNS Threshold SHDN = 0, JKSNS JACKSNS Sense Voltage JACKSNS Sense Current BATTERY ADC Input Voltage Range LSB Size 2.6 0.1 5.6 V V SHDN = 0 VJACKSNS = 0V 0.92 x VMICBIAS 0.95 x VMICBIAS 0.98 x VMICBIAS V RON THD+N 2 60 84 +15 I % dB FA
SPKLVDD - 0.7 SPKLVDD 4 10 V FA
DIGITAL INPUT/OUTPUT CHARACTERISTICS
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER MCLK Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance SDINS1, BCLKS1, LRCLKS1--INPUT Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance IIH, IIL VDVDDS1 = 3.6V, VIN = 0V, 3.6V; TA = +25C -1 10 VIH VIL 200 +1 0.7 x DVDDS1 0.29 x DVDDS1 V V mV FA pF 19 VIH VIL IIH, IIL VDVDD = 2.0V, VIN = 0V, 5.5V; TA = +25C -1 10 1.2 0.6 +1 V V FA pF SYMBOL CONDITIONS MIN TYP MAX UNITS
Stereo Audio Codec with FLEXSOUND Technology MAX98088
DIGITAL INPUT/OUTPUT CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER Output Low Voltage Output High Voltage Input Leakage Current SYMBOL VOL VOH IIH, IIL CONDITIONS VDVDDS1 = 1.65V, IOL = 3mA VDVDDS1 = 1.65V, IOH = 3mA VDVDD = 2.0V, VIN = 0V, 5.5V; TA = +25C, high-impedance state DVDDS1 - 0.4 -1 +1 MIN TYP MAX 0.4 UNITS V V FA BCLKS1, LRCLKS1, SDOUTS1--OUTPUT
SDINS2, BCLKS2, LRCLKS2--INPUT Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance BCLKS2, LRCLKS2, SDOUTS2--OUTPUT Output Low Voltage Output High Voltage Input Leakage Current SDA, SCL--INPUT Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance SDA, IRQ--OUTPUT Output High Current Output Low Voltage DIGMICDATA--INPUT Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance IIH, IIL VDVDD = 2.0V, VIN = 0V, 2.0V; TA = +25C -25 10 VIH VIL 125 +25 0.65 x DVDD 0.35 x DVDD V V mV FA pF IOH VOL VOUT = 5.5V, TA = +25C VDVDD = 1.65V, IOL = 3mA IIH, IIL VDVDD = 2.0V, VIN = 0V, 5.5V; TA = +25NC -1 10 1 0.2 x DVDD VIH VIL 210 +1 0.7 x DVDD 0.3 x DVDD V V mV FA pF mA V VOL VOH IIH, IIL VDVDDS2 = 1.65V, IOL = 3mA VDVDDS2 = 1.65V, IOH = 3mA VDVDD = 2.0V, VIN = 0V, 5.5V; TA = +25NC, high-impedance state DVDDS2 - 0.4 -1 +1 0.4 V V FA IIH, IIL VDVDDS2 = 3.6V, VIN = 0V, 3.6V; TA = +25C -1 10 VIH VIL 200 +1 0.7 x DVDDS2 0.29 x DVDDS2 V V mV FA pF
20
Stereo Audio Codec with FLEXSOUND Technology
DIGITAL INPUT/OUTPUT CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER DIGMICCLK--OUTPUT Output Low Voltage Output High Voltage VOL VOH VDVDD = 1.65V, IOL = 1mA VDVDD = 1.65V, IOH = 1mA DVDD 0.4 0.4 V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX98088
INPUT CLOCK CHARACTERISTICS
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER MCLK Input Frequency MCLK Input Duty Cycle Maximum MCLK Input Jitter LRCLK Sample Rate (Note 8) DAI1 LRCLK Average Frequency Error (Note 9) DAI2 LRCLK Average Frequency Error (Note 9) PLL Lock Time Maximum LRCLK Jitter to Maintain PLL Lock Soft-Start/Stop Time 10 Rapid lock mode Nonrapid lock mode DHF_ = 0 DHF_ = 1 FREQ1 = 0x8 to 0xF FREQ1 = 0x0 8 48 0 -0.025 -0.025 2 12 SYMBOL fMCLK PSCLK = 01 PSCLK = 10 or 11 CONDITIONS MIN 10 40 30 100 48 96 0 +0.025 +0.025 7 25 100 50 TYP MAX 60 60 70 UNITS MHz % psRMS kHz % % ms ns ms
21
Stereo Audio Codec with FLEXSOUND Technology MAX98088
AUDIO INTERFACE TIMING CHARACTERISTICS
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER BCLK Cycle Time BCLK High Time BCLK Low Time BCLK or LRCLK Rise and Fall Time SDIN to BCLK Setup Time LRCLK to BCLK Setup Time SDIN to BCLK Hold Time LRCLK to BCLK Hold Time Minimum Delay Time from LSB BCLK Falling Edge to High-Impedance State LRCLK Rising Edge to SDOUT MSB Delay BCLK to SDOUT Delay SYMBOL tBCLK tBCLKH tBCLKL tR, tF tSETUP tSYNCSET tHOLD tSYNCHOLD Slave mode tHIZOUT Master mode, TDM_ = 1 Slave mode Slave mode Slave mode Slave mode Master mode, CL = 15pF 20 20 20 20 42 CONDITIONS MIN 90 20 20 TYP MAX UNITS ns ns ns ns ns ns ns ns ns
tSYNCTX tCLKTX
CL = 30pF, TDM_ = 1, FSW_ = 1 CL = 30pF Master mode Master mode TDM_ = 1, BCLK rising edge TDM_ = 0 TDM_ = 1 TDM_ = 0 TDM_ = 1, FSW_ = 1 20 -15
50 50 50 +15 0.8 x tBCLKL
ns ns
Delay Time from BCLK to LRCLK Delay Time from LRCLK to BCLK After LSB
tCLKSYNC
ns
tENDSYNC
ns
t BCLK R (OUTPUT) LRCLK (OUTPUT)
tF
tBCLK BCLK (INPUT) tSYNCSET LRCLK (INPUT) tBCLKH tBCLKL
tCLKSYNC
tHIZOUT SDOUT (OUTPUT) SDIN (INPUT) LSB HI-Z
tCLKTX tSETUP MSB tHOLD SDOUT (OUTPUT) SDIN (INPUT) LSB
tHIZOUT HI-Z
tCLKTX tSETUP MSB tHOLD
LSB MASTER MODE
MSB
LSB SLAVE MODE
MSB
Figure 1. Non-TDM Audio Interface Timing Diagrams (TDM_ = 0)
22
Stereo Audio Codec with FLEXSOUND Technology MAX98088
tBCLK tF BCLK (OUTPUT) tCLKSYNC LRCLK (OUTPUT) tHIZOUT SDOUT (OUTPUT) LSB tCLKTX HI-Z MSB tSETUP tHOLD SDIN (INPUT) LSB MSB MASTER MODE SDIN (INPUT) LSB MSB SLAVE MODE tCLKSYNC tR BCLK (INPUT) tSYNCSET LRCLK (INPUT) tHIZOUT SDOUT (OUTPUT) LSB tCLKTX HI-Z MSB tSETUP tHOLD tSYNCHOLD tBCLKH tBCLKL
Figure 2. TDM Audio Interface Timing Diagram (TDM_ = 1, FSW_ = 0)
tBCLK tF BCLK (OUTPUT) tENDSYNC LRCLK (OUTPUT) tHIZOUT SDOUT (OUTPUT) LSB tSYNCTX HI-Z tCLKTX MSB tSETUP tHOLD SDIN (INPUT) LSB MSB MASTER MODE SDIN (INPUT) LSB MSB SLAVE MODE tCLKSYNC LRCLK (INPUT) tHIZOUT SDOUT (OUTPUT) LSB tSYNCTX HI-Z tCLKTX MSB tSETUP tHOLD tR BCLK (INPUT) tBCLKH tBCLKL
Figure 3. TDM Audio Interface Timing Diagram (TDM_ = 1, FSW_ = 1)
DIGITAL MICROPHONE TIMING CHARACTERSTICS
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER DIGMICCLK Frequency DIGMICDATA to DIGMICCLK Setup Time DIGMICDATA to DIGMICCLK Hold Time SYMBOL fMICCLK tSU,MIC tHD,MIC MICCLK = 00 MICCLK = 01 Either clock edge Either clock edge 20 0 CONDITIONS MIN TYP MCLK/8 MCLK/6 MAX UNITS MHz ns ns
23
Stereo Audio Codec with FLEXSOUND Technology MAX98088
1/fMICCLK
tHD,MIC tSU,MIC tHD,MIC tSU,MIC
LEFT
RIGHT
LEFT
RIGHT
Figure 4. Digital Microphone Timing Diagram
I2C TIMING CHARACTERSTICS
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER Serial-Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition SCL Pulse-Width Low SCL Pulse-Width High Setup Time for a Repeated START Condition Data Hold Time Data Setup Time SDA and SCL Receiving Rise Time SDA and SCL Receiving Fall Time SDA Transmitting Fall Time Setup Time for STOP Condition Bus Capacitance Pulse Width of Suppressed Spike SYMBOL fSCL tBUF tHD,STA tLOW tHIGH tSU,STA tHD,DAT tSU,DAT tR tF tF tSU,STO CB tSP Guaranteed by SDA transmitting fall time 0 RPU = 475I, CB = 100pF, 400pF (Note 10) (Note 10) RPU = 475I, CB = 100pF, 400pF (Note 10) CONDITIONS Guaranteed by SCL pulse-width low and high MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 20 + 0.05CB 0.6 400 50 300 300 250 900 TYP MAX 400 UNITS kHz Fs Fs Fs Fs Fs ns ns ns ns ns Fs pF ns
24
Stereo Audio Codec with FLEXSOUND Technology
I2C TIMING CHARACTERISTICS (continued)
(VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. TA = +25NC, unless otherwise noted.) (Note 1)
MAX98088
SDA tSU,DAT tHD,DAT tHIGH tSU,STA tBUF tHD,STA tSP tSU,STO
tLOW SCL tHD,STA START CONDITION
tR
tF REPEATED START CONDITION STOP CONDITION START CONDITION
Figure 5. I2C Interface Timing Diagram Note 1: The IC is 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design. Note 2: Analog supply current = IAVDD + IHPVDD. Speaker supply current = ISPKLVDD + ISPKRVDD. Digital supply current = IDVDD + IDVDDS1 + IDVDDS2. Note 3: Clocking all zeros into the DAC. Note 4: Dynamic range measured using the EIAJ method. -60dBFS, 1kHz output signal, A-weighted and normalized to 0dBFS. f = 20Hz to 20kHz. Note 5: Gain measured relative to the 0dB setting. Note 6: The filter specification is accurate only for synchronous clocking modes, where NI is a multiple of 0x1000. Note 7: 0dBFS for DAC input. 1VP-P for INA/INB inputs. Note 8: LRCLK may be any rate in the indicated range. Asynchronous or noninteger MCLK/LRCLK ratios may exhibit some fullscale performance degradation compared to synchronous integer related MCLK/LRCLK ratios. Note 9: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate. Note 10: CB is in pF.
Power Consumption
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.8V, VSPKLVDD = VSPKRVDD = 3.7V) MODE Playback to Headphone Only DAC Playback 48kHz Stereo HP DAC HP Low power mode, 24-bit, music filters, 256Fs DAC Playback 48kHz Stereo HP DAC HP Low power mode, 24-bit, music filters, 256Fs, 0.1mW/channel, RHP = 32I 1.25 0.47 0.00 1.35 0.01 5.55 97 IAVDD (mA) IPVDD (mA) ISPKVDD + ISPKLVDD (mA) IDVDD (mA) IDVDDS1 + IDVDDS2 (mA) POWER (W) DYNAMIC RANGE (dB)
1.25
1.81
0.00
1.56
0.01
8.32
97
25
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Power Consumption (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.8V, VSPKLVDD = VSPKRVDD = 3.7V) MODE DAC Playback 48kHz Stereo HP DAC HP 24-bit, music filters, 256Fs DAC Playback 48kHz Stereo HP DAC HP 24-bit, music filters, 256Fs, 0.1mW/ channel, RHP = 32I DAC Playback 44.1kHz Stereo HP DAC HP 24-bit, music filters DAC Playback 44.1kHz Stereo HP DAC HP Low power mode, 24-bit, music filters DAC Playback 8kHz Stereo HP DAC HP 16-bit, voice filters DAC Playback 8kHz Stereo HP DAC HP 16-bit, low power mode, voice filters DAC Playback 8kHz Mono HP DAC HP 16-bit, low power mode, voice filters Line Playback Stereo HP INA HP Single-ended inputs DAC Playback to Class D Speaker DAC Playback 48kHz Stereo SPK DAC SPK 24-bit, music filters 2.31 0.00 6.33 2.14 0.01 31.44 86 IAVDD (mA) 2.04 IPVDD (mA) 1.27 ISPKVDD + ISPKLVDD (mA) 0.00 IDVDD (mA) 1.53 IDVDDS1 + IDVDDS2 (mA) 0.01 POWER (W) 8.72 DYNAMIC RANGE (dB) 101
2.04
2.11
0.00
1.74
0.01
10.63
101
2.03
1.27
0.00
1.41
0.01
8.46
100
1.25
0.47
0.00
1.25
0.01
5.34
97
2.04
1.27
0.00
1.07
0.00
7.89
95
1.26
0.47
0.00
0.90
0.00
4.72
94
0.77
0.29
0.00
0.79
0.00
3.33
93.7
2.40
1.27
0.00
0.02
0.00
6.67
95
26
Stereo Audio Codec with FLEXSOUND Technology
Power Consumption (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.8V, VSPKLVDD = VSPKRVDD = 3.7V) MODE DAC Playback 48kHz Mono SPK DAC SPK 24-bit, music filters Line Playback Mono SPK INA SPKL Differential inputs Full Duplex Full-Duplex 8kHz Mono RCV MIC1 ADC DAC REC 16-bit, voice filters Full-Duplex 8kHz Stereo HP MIC1/2 ADC DAC HP 16-bit, mixer, voice filters Full-Duplex 8kHz Stereo HP MIC1/2 ADC DAC HP 16-bit, low power mode, voice filters Line Record Line Stereo Record 48kHz INA ADC 24-bit, low power, music filters Line Stereo Record 48kHz INA ADC Direct pin input, 24bit, low power, music filters 6.19 0.00 0.20 1.31 0.15 14.47 91 6.32 0.00 1.54 1.24 0.01 19.33 Record = 87 Playback = 94 IAVDD (mA) 1.35 IPVDD (mA) 0.00 ISPKVDD + ISPKLVDD (mA) 3.23 IDVDD (mA) 1.84 IDVDDS1 + IDVDDS2 (mA) 0.01 POWER (W) 17.69 DYNAMIC RANGE (dB) 86
MAX98088
1.01
0.00
3.24
0.03
0.00
13.83
83
11.19
1.27
0.48
1.28
0.01
26.43
Record = 87 Playback = 96
7.12
0.47
0.48
1.10
0.02
17.44
Record = 87 Playback = 94
5.69
0.00
0.20
1.31
0.12
13.53
93
27
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Typical Operating Characteristics
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
Microphone to ADC
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC)
MAX98088 toc01
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC)
MAX98088 toc02
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC)
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 -100 10 100 1000 FREQUENCY (Hz) 10,000 100,000
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 -100 10
THD+N RATIO (dB)
MCLK = 13MHz LRCLK = 8kHz FREQ MODE VIN = 1VP-P AVMICPRE_ = 0dB
-10 -20 -30 -40 -50 -60 -70 -80
MCLK = 13MHz LRCLK = 44.1kHz PLL MODE VIN = 1VP-P AVMICPRE_ = 0dB
MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 1VP-P AVMICPRE_ = 0dB
100
1000
10,000
-90
10
100
1000 FREQUENCY (Hz)
10,000
100,000
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC)
MAX98088 toc04
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC)
MAX98088 toc05
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC)
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 -100
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 -100 10
THD+N RATIO (dB)
MCLK = 12.288MHz LRCLK = 96kHz NI MODE VIN = 1VP-P AVMICPRE_ = 0dB
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100
MCLK = 13MHz LRCLK = 8kHz FREQ MODE VIN = 0.1VP-P AVMICPRE_ = 0dB
MCLK = 13MHz LRCLK = 8kHz FREQ MODE VIN = 0.032VP-P AVMICPRE_ = 0dB
100
1000 FREQUENCY (Hz)
10,000
100,000
10
100
1000
10,000
10
100
1000
10,000
FREQUENCY (Hz)
FREQUENCY (Hz)
28
MAX98088 toc06
0
0
0
MAX98088 toc03
0
0
0
Stereo Audio Codec with FLEXSOUND Technology
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
MAX98088
GAIN vs. FREQUENCY (MIC TO ADC)
MAX98088 toc07
COMMON-MODE REJECTION RATIO vs. FREQUENCY (MIC TO ADC)
MAX98088 toc08
POWER-SUPPLY RECTION RATIO vs. FREQUENCY (MIC TO ADC)
0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 -90 10 100 1000 FREQUENCY (Hz) 10,000 100,000 RIPPLE ON AVDD, DVDD, HPVDD INPUTS AC GROUNDED VRIPPLE = 200mVP-P
MAX98088 toc09 MAX98088 toc12
10 0 NORMALIZED GAIN (dBr1) -10 -20 -30 -40 -50 -60 -70 -80 -90 10 100 1000
70 60 50 CMRR (dB) 40 30 20 10 0 MICPRE = 0dB MICPRE = 20dB
MICPRE = 30dB
10
MODE = 1
MODE = 0 MCLK = 13MHz LRCLK = 8kHz FREQ MODE VIN = 1VP-P AVMICPRE_ = 0dB
10,000
MCLK = 12.288MHz LRCLK = 48kHz FREQ MODE 10 100 1000 FREQUENCY (Hz) 10,000 100,000
RIPPLE ON SPKLVDD, SPKRVDD
FREQUENCY (Hz)
FFT, 0dBFS (MIC TO ADC)
MAX98088 toc10
FFT, -60dBFS (MIC TO ADC)
-20 -40 AMPLITUDE (dBFS) -60 -80 -100 -120 -140 -160 -180
FFT, 0dBFS (MIC TO ADC)
MAX98088 toc11
20 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 -160 -180 0
AMPLITUDE (dBFS)
MCLK = 13MHz LRCLK = 8kHz FREQ MODE AVMICPRE_ = 0dB
0
MCLK = 13MHz LRCLK = 8kHz FREQ MODE AVMICPRE_ = 0dB
20 0 -20 -40 -60 -80 -100 -120 -140
MCLK = 13MHz LRCLK = 44.1kHz PLL MODE AVMICPRE_ = 0dB
500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (Hz)
0
500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (Hz)
0
5000
10,000 FREQUENCY (Hz)
15,000
20,000
29
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
FFT, -60dBFS (MIC TO ADC)
MAX98088 toc13
FFT, 0dBFS (MIC TO ADC)
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140
-20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 0 5000 10,000
MCLK = 13MHz LRCLK = 44.1kHz PLL MODE AVMICPRE_ = 0dB
MCLK = 12.288MHz LRCLK = 48kHz NI MODE AVMICPRE_ = 0dB
15,000
20,000
0
5000
10,000 FREQUENCY (Hz)
15,000
20,000
FREQUENCY (Hz)
FFT, -60dBFS (MIC TO ADC)
MAX98088 toc15
FFT, 0dBFS (MIC TO ADC)
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140
-20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 0 5000
MCLK = 12.288MHz LRCLK = 48kHz NI MODE AVMICPRE_ = 0dB
MCLK = 12.288MHz LRCLK = 96kHz NI MODE AVMICPRE_ = 0dB
10,000 FREQUENCY (Hz)
15,000
20,000
0
5000
10,000 FREQUENCY (Hz)
15,000
20,000
30
MAX98088 toc16
0
20
MAX98088 toc14
0
20
Stereo Audio Codec with FLEXSOUND Technology
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
MAX98088
FFT, -60dBFS (MIC TO ADC)
-20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000
ADC ENABLE/DISABLE RESPONSE (MIC TO ADC)
MAX98088 toc18 MAX98088 toc17
0
MCLK = 12.288MHz LRCLK = 96kHz NI MODE AVMICPRE_ = 0dB
SCL 1V/div
ADC OUTPUT 0.5V/div
10ms/div
SOFTWARE TURN-ON/OFF RESPONSE (MIC TO ADC)
MAX98088 toc19
SCL 1V/div
ADC OUTPUT 0.5V/div
10ms/div
31
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
Line to ADC
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC)
MAX98088 toc20
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC)
MAX98088 toc21
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC)
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 0.1VP-P AVPGAIN_ = +20dB CIN = 1F
MAX98088 toc22
0 -10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 10 100 1000
THD+N RATIO (dB)
MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 1.4VP-P AVPGAIN_ = -6dB CIN = 1F
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 1VP-P AVPGAIN_ = 0dB CIN = 1F
0
10,000
100,000
10
100
1000 FREQUENCY (Hz)
10,000
100,000
10
100
1000 FREQUENCY (Hz)
10,000
100,000
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE-IN TO ADC)
MAX98088 toc23
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (LINE-IN TO ADC)
0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 -90 RIPPLE ON SPKLVDD, SPKRVDD 10 100 1000 FREQUENCY (Hz) 10,000 100,000 RIPPLE ON AVDD, DVDD, HPVDD VRIPPLE = 200mVP-P
MAX98088 toc24
0 -10 -20 -30 THD+N (dB) -40 -50 -60 -70 -80 -90 10 100
MCLK = 12.288MHz LRCLK = 48kHz VIN = 1VRMS EXTERNAL GAIN MODE RIN = 56kI CIN = 1F
10
1000 FREQUENCY (Hz)
10,000
100,000
32
Stereo Audio Codec with FLEXSOUND Technology
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
MAX98088
Line-In Pin Direct to ADC
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE-IN DIRECT TO ADC)
MAX98088 toc25
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (LINE-IN DIRECT TO ADC)
-10 -20 PSRR (dBr1) -30 -40 -50 -60 -70 -80 -90 RIPPLE ON SPKLVDD, SPKRVDD 10 100 1000 FREQUENCY (Hz) 10,000 100,000 RIPPLE ON AVDD, DVDD, HPVDD VRIPPLE = 200mVP-P
MAX98088 toc26 MAX98088 toc28
0 -10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 -100 10 100 1000
MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 1VP-P CIN = 1F
0
10,000
100,000
FREQUENCY (Hz)
Digital Loopback
FFT, 0dBFS (SDINS1 TO SDINS2 DIGITAL LOOPBACK)
-20 -40 AMPLITUDE (dBFS) -60 -80 -100 -120 -140 -160 -180 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000 MCLK = 12.288MHz LRCLK = 48kHz NI MODE
MAX98088 toc27
FFT, -60dBFS (SDINS1 TO SDINS2 DIGITAL LOOPBACK)
0 -20 -40 AMPLITUDE (dBFS) -60 -80 -100 -120 -140 -160 -180 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000 MCLK = 12.288MHz LRCLK = 48kHz NI MODE
0
33
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
Analog Loopback
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC TO DAC TO HEADPHONE)
MAX98088 toc29
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC TO DAC TO HEADPHONE)
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70
FFT, 0dBFS (LINE TO ADC TO DAC TO HEADPHONE)
MAX98088 toc30
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 10
AMPLITUDE (dBV)
MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I CIN = 1F
MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I CIN = 1F
0 -20 -40 -60 -80 -100 -120
MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I CIN = 1F
POUT = 0.020W
POUT = 0.020W
POUT = 0.01W
100 1000 FREQUENCY (Hz) 10,000 100,000
-80
POUT = 0.01W
10 100 1000 FREQUENCY (Hz) 10,000 100,000
-140 0 5000 10,000 FREQUENCY (kHz) 15,000 20,000
FFT, -60dBFS (LINE TO ADC TO DAC TO HEADPHONE)
MAX98088 toc32
FFT, 0dBFS (LINE TO ADC TO DAC TO HEADPHONE)
MAX98088 toc33
FFT, -60dBFS (LINE TO ADC TO DAC TO HEADPHONE)
-20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140
-20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140 0 5000 10,000
AMPLITUDE (dBV)
MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I CIN = 1F
0 -20 -40 -60 -80 -100 -120 -140
MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I CIN = 1F
MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I CIN = 1F
15,000
20,000
0
5000
10,000 FREQUENCY (Hz)
15,000
20,000
0
5000
10,000 FREQUENCY (Hz)
15,000
20,000
FREQUENCY (Hz)
34
MAX98088 toc34
0
20
0
MAX98088 toc31
0
0
20
Stereo Audio Codec with FLEXSOUND Technology
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
MAX98088
DAC to Receiver
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO RECEIVER)
MAX98088 toc35
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO RECEIVER)
OUTPUT POWER PER CHANNEL (mW) -10 -20 -30 THD+N (dB) MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I AVREC = +8dB
MAX98088 toc36
OUTPUT POWER vs. SUPPLY VOLTAGE (DAC TO RECEIVER)
180 160 140 120 100 80 60
-10 -20 -30 THD+N (dB) -40 -50 -60 -70 -80 -90 0
MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I AVREC = +8dB f = 3000Hz f = 1000Hz
MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I AVREC = +8dB THD+N = 10%
-40 -50 -60 -70 POUT = 0.02W
THD+N = 1%
f = 100Hz 0.02 0.04 0.06 0.08 0.10 0.12
-80 -90 10 100
POUT = 0.08W 1000 10,000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
OUTPUT POWER (W)
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
GAIN vs. FREQUENCY (DAC TO RECEIVER)
MAX98088 toc38
POWER CONSUMPTION vs. OUTPUT POWER (DAC TO RECEIVER)
MAX98088 toc39
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO RECEIVER)
-10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 RIPPLE ON SPKLVDD, SPKRVDD RIPPLE ON AVDD, DVDD, HPVDD INPUTS AC GROUNDED VRIPPLE = 200mVP-P
MAX98088 toc40
5 4 NORMALIZED GAIN (dBrA) 3 2 1 0 -1 -2 -3 -4 -5 10 100 1000
250 200 150 100 50 0 0 10 20 30 40 50
0
10,000
POWER CONSUMPTION (mW)
MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I
MCLK = 13MHz LRCLK = 8kHz FREQ MODE AVREC = +8dB RREC = 32I
60
10
100
1000 FREQUENCY (Hz)
10,000
100,000
FREQUENCY (Hz)
OUTPUT POWER PER CHANNEL (mW)
MAX98088 toc37
0
0
200
35
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
SOFTWARE TURN-ON/OFF RESPONSE (DAC TO RECEIVER, VSEN = 0)
MAX98088 toc41
SOFTWARE TURN-ON/OFF RESPONSE (DAC TO RECEIVER, VSEN = 1)
MAX98088 toc42
FFT, 0dBFS (DAC TO RECEIVER)
0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140 -160
SCL 1V/div
SCL 1V/div
MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I
RECEIVER OUTPUT 1V/div
RECEIVER OUTPUT 1V/div
10ms/div
10ms/div
0
5
10 FREQUENCY (kHz)
15
20
FFT, -60dBFS (DAC TO RECEIVER)
MAX98088 toc44
WIDEBAND FFT, 0dBFS (DAC TO RECEIVER)
MAX98088 toc45
WIDEBAND FFT, 0dBFS (DAC TO RECEIVER)
MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I
MAX98088 toc46
0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140 0 5 10 FREQUENCY (kHz) 15
0 -20 AMPLITUDE (dBm) -40 -60 -80 -100 -120
AMPLITUDE (dBm)
MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I
MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I
0 -20 -40 -60 -80 -100 -120
20
0
1
10
100
1000
10,000
0
1
10
100
1000
10,000
FREQUENCY (kHz)
FREQUENCY (kHz)
36
MAX16067 toc43
20
Stereo Audio Codec with FLEXSOUND Technology
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
MAX98088
Line to Receiver
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (LINE TO RECEIVER)
MAX98088 toc47
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO RECEIVER)
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 POUT = 0.08W 10 100 1000 FREQUENCY (Hz) 10,000 100,000 POUT = 0.02W RREC = 32I AVREC = +8dB CIN = 1F
MAX98088 toc48
0 -10 THD+N RATIO (dB) -20 -30 -40 -50 -60 -70 0
RREC = 32I AVREC = +8dB CIN = 1F
0
f = 100Hz
f = 1000Hz
f = 6000Hz
0.02
0.04
0.06
0.08
0.10
-90
OUTPUT POWER (W)
GAIN vs. FREQUENCY (LINE TO RECEIVER)
MAX98088 toc49
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (LINE-IN DIRECT TO RECEIVER)
-10 -20 PSRR (dBr1) -30 -40 -50 -60 -70 -80 RIPPLE ON SPKLVDD, SPKRVDD RIPPLE ON AVDD, DVDD, HPVDD INPUTS AC GROUNDED VRIPPLE = 200mVP-P
MAX98088 toc50
5 4 NORMALIZED GAIN (dBrA) 3 2 1 0 -1 -2 -3 -4 -5 10 100 1000 FREQUENCY (Hz) 10,000
0
RREC = 32I CIN = 1F
100,000
-90 10 100 1000 FREQUENCY (Hz) 10,000 100,000
37
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
DAC to Line Output
FFT, 0dBFS (DAC TO LINE OUT)
MAX98088 toc51
FFT, -60dBFS (DAC TO LINE OUT)
-20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RLOAD = 10kI
MAX98088 toc52
20 0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140 0 5000 10,000 FREQUENCY (Hz) 15,000 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RLOAD = 10kI
0
20,000
Line to Line Output
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT LEVEL (LINE-IN TO LINE-OUT)
MAX98088 toc53
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE-IN TO LINE-OUT)
-10 -20 -30 THD+N (dB) -40 -50 -60 -70
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE-IN TO LINE-OUT)
MAX98088 toc54
-10 -20 -30 THD+N (dB) -40 -50 -60 -70 -80 -90 0
RLOAD = 10kI
RLOAD = 10kI
-10 -20 -30 THD+N (dB) -40 -50 -60 -70 -80 -90 -100
VIN = 1VRMS, 1kHz RLOAD = 10kI EXTERNAL GAIN MODE REXT = 56kI
f = 6kHz
VOUT = 0.2VRMS
f = 1kHz
0.2 0.4 0.6
f = 100Hz
0.8 1.0 1.2 1.4
-80 -90 10
VOUT = 0.8VRMS
100 1000 FREQUENCY (Hz) 10,000 100,000
10
100
1000 FREQUENCY (Hz)
10,000
100,000
OUTPUT LEVEL (VRMS)
38
MAX98088 toc55
0
0
0
Stereo Audio Codec with FLEXSOUND Technology
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
MAX98088
DAC to Speaker
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER)
MAX98088 toc56
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER)
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 0
VSPK_VDD = 4.2V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSPK_ = 8I + 68H AVSPK_ = +8dB f = 6000Hz f = 1000Hz
VSPK_VDD = 3.7V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 8I + 68H AVSPK_ = +8dB f = 6000Hz
f = 1000Hz
f = 100Hz
0.2 0.4 0.6 0.8 1.0 1.2
-80 -90 0 0.2 0.4
f = 100Hz
0.6 0.8 1.0
OUTPUT POWER (W)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER)
MAX98088 toc58
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER)
MAX98088 toc59
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER)
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 0
THD+N RATIO (dB)
VSPK_VDD = 3V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSPK_ = 8I + 68H AVSPK_ = +8dB f = 6000Hz f = 1000Hz
-10 -20 -30 -40 -50 -60 -70
VSPK_VDD = 4.2V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 4I + 33H AVSPK_ = +8dB
VSPK_VDD = 3.7V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 4I + 33H AVSPK_ = +8dB f = 6000Hz f = 1000Hz
f = 6000Hz
f = 100Hz
0.1 0.2 0.3 0.4 0.5 0.6
-80 -90 0
f = 100Hz f = 1000Hz
0.5 1.0 1.5 2.0 2.5 OUTPUT POWER (W)
-70 -80 0 0.5
f = 100Hz
1.0 OUTPUT POWER (W) 1.5 2.0
OUTPUT POWER (W)
39
MAX98088 toc60
0
0
0
MAX98088 toc57
0
0
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER)
MAX98088 toc61
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO SPEAKER)
MAX98088 toc62
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO SPEAKER)
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60
-10 THD+N RATIO (dB) -20 -30 -40 -50 -60 -70 0
THD+N RATIO (dB)
VSPK_VDD = 3V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 4I + 33H AVSPK_ = +8dB f = 6000Hz
-10 -20 -30 -40 -50 -60
VSPK_VDD = 4.2V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 8I + 68H AVSPK_ = +8dB
VSPK_VDD = 3.7V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 8I + 68H AVSPK_ = +8dB
POUT = 0.55W
POUT = 0.55W
f = 100Hz
0.2 0.4 0.6
f = 1000Hz
0.8 1.0 1.2
-70 -80 20 200
POUT = 0.25W
2000 20,000
-70 -80 20 200
POUT = 0.25W
2000 20,000
OUTPUT POWER (W)
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO SPEAKER)
MAX98088 toc64
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO SPEAKER)
OUTPUT POWER PER CHANNEL (mW) -10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80
OUTPUT POWER vs. SUPPLY VOLTAGE (DAC TO SPEAKER)
MAX98088 toc65
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 100
VSPK_VDD = 4.2V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 4I + 33H AVSPK_ = +8dB
POUT = 1W
VSPK_VDD = 3.7V MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSP_ = 4I + 33H AVSPK_ = +8dB
2000 1800 1600 1400 1200 1000 800 600 400 2.5
POUT = 1W
MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSPK_ = 8I + 68H AVSPK_ = +8dB THD+N = 10%
POUT = 0.5W
POUT = 0.5W
THD+N = 1%
1000
10,000
100,000
-90 100 1000 10,000 100,000 FREQUENCY (Hz)
3.0
3.5
4.0
4.5
5.0
5.5
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
40
MAX98088 toc66
0
0
2200
MAX98088 toc63
0
0
0
Stereo Audio Codec with FLEXSOUND Technology
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
MAX98088
OUTPUT POWER vs. SUPPLY VOLTAGE (DAC TO SPEAKER)
MAX98088 toc67
GAIN vs. FREQUENCY (DAC TO SPEAKER)
MAX98088 toc68
EFFICIENCY vs. OUTPUT POWER (DAC TO SPEAKER)
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 ZSPK = 4I + 33H VSPK_VDD = 4.2V MCLK = 12.288MHz LRCLK = 48kHz NI MODE AVSKP_ = +8dB 0 0.5 1.0 1.5 2.0 2.5 ZSPK = 8I + 68H
MAX98088 toc69
4000 OUTPUT POWER PER CHANNEL (mW) 3500 3000 2500 2000 1500 1000 500 0 2.5
NORMALIZED GAIN (dBrA)
MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSPK_ = 4I + 33H AVSPK_ = +8dB THD+N = 10%
5 4 3 2 1 0 -1 -2 -3 -4 -5
100
MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSPK_ = 8I + 68H
THD+N = 1%
3.0
3.5
4.0
4.5
5.0
5.5
100
1000
10,000
100,000
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
OUTPUT POWER (W)
EFFICIENCY vs. OUTPUT POWER (DAC TO SPEAKER)
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 OUTPUT POWER (W) ZSPK = 4I + 33H VSPK_VDD = 3.7V MCLK = 12.288MHz LRCLK = 48kHz NI MODE AVSKP_ = +8dB ZSPK = 8I + 68H
MAX98088 toc70
SUPPLY CURRENT vs. SUPPLY VOLTAGE (DAC TO SPEAKER)
MAX98088 toc71
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO SPEAKER)
-10 -20 PSRR (dB) -30 -40 -50 -60 RIPPLE ON AVDD, DVDD, HPVDD VRIPPLE = 200mVP-P
MAX98088 toc72
100
18 15 SUPPLY CURRENT (mA) 12 9 6 3 0 2.5 3.0 3.5 4.0 4.5 5.0 MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSPK_ = 8I + 68H SPKVOL_ = +8dB ALL ZEROS AT INPUT
0
-70 -80 5.5 10 100
RIPPLE ON SPKLVDD, SPKRVDD 1000 FREQUENCY (Hz) 10,000 100,000
SUPPLY VOLTAGE (V)
41
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
CROSSTALK vs. FREQUENCY (DAC TO SPEAKER)
-10 -20 CROSSTALK (dB) -30 -40 -50 -60 -70 -80 10 100 1000 FREQUENCY (Hz) 10,000 100,000
SOFTWARE TURN-ON/OFF RESPONSE (DAC TO SPEAKER, VSEN = 0)
MAX98088 toc74 MAX98088 toc73
SOFTWARE TURN-ON/OFF RESPONSE (DAC TO SPEAKER, VSEN = 1)
MAX98088 toc75
0
MCLK = 12.288MHz LRCLK = 48kHz NI MODE ZSPK_ = 8I + 68H
SCL 1V/div
SCL 1V/div
SPEAKER OUTPUT 1V/div
SPEAKER OUTPUT 1V/div
10ms/div
10ms/div
FFT, -60dBFS (DAC TO SPEAKERS)
MAX98088 toc76
FFT, -60dBFS (DAC TO SPEAKERS)
MAX98088 toc77
WIDEBAND FFT (DAC TO SPEAKER)
-10 -20 AMPLITUDE (dBm) -30 -40 -50 -60 -70 -80 -90 -100 1 10 FREQUENCY (MHz) 100 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE ZSPK_ = 8I + 68H
MAX98088 toc78
20 0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140 0 5000 10,000 FREQUENCY (kHz) 15,000
0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140
0
MCLK = 12.2888MHz LRCLK = 48kHz NI MODE ZSPK_ = 8I + 68H
MCLK = 13MHz LRCLK = 44.1kHz PLL MODE ZSPK_ = 8I + 68H
20,000
0
5000
10,000 FREQUENCY (kHz)
15,000
20,000
42
Stereo Audio Codec with FLEXSOUND Technology
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
MAX98088
Line to Speaker
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (LINE TO SPEAKER)
MAX98088 toc79
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO SPEAKER)
MAX98088 toc80
GAIN vs. FREQUENCY (LINE TO SPEAKER)
4 NORMALIZED GAIN (dBrA) 3 2 1 0 -1 -2 -3 -4 -5
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 0
ZSPK = 8I + 68H AVSPK_ = +8dB CIN = 1F
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70
ZSPK = 8I + 68H AVSPK_ = +8dB CIN = 1F
ZFN = 8I + 68H CIN = 1F
f = 6000Hz
f = 1000Hz
POUT = 0.5W
f = 100Hz
0.2 0.4 0.6 0.8 1.0 OUTPUT POWER (W)
POUT = 0.25W
10 100 1000 FREQUENCY (Hz) 10,000 100,000
-80
10
100
1000 FREQUENCY (Hz)
10,000
100,000
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (LINE-IN TO SPEAKER)
MAX98088 toc82
CROSSTALK vs. FREQUENCY (LINE TO SPEAKER)
-10 -20 CROSSTALK (dB)
0 -10 -20 PSRR (dBr1) -30 -40 -50 -60 -70 -80 -90 10
INPUTS AC GROUNDED VRIPPLE = 200mVP-P
ZFN = 8I + 68H CIN = 1F
RIPPLE ON SPKLVDD, SPKRVDD
-30 -40 -50 -60 -70
RIPPLE ON AVDD, DVDD, HPVDD 100 1000 FREQUENCY (Hz) 10,000 100,000
RIGHT TO LEFT LEFT TO RIGHT
10 100 1000 FREQUENCY (Hz) 10,000 100,000
-80
MAX98088 toc83
10
0
MAX98088 toc81
0
0
5
43
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
DAC to Headphone
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE)
MAX98088 toc84
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE)
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 f = 100Hz f = 6000Hz f = 1000Hz MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I AVHP_ = +3dB
MAX98088 toc85
0 -10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 0
MCLK = 13MHz LRCLK = 8kHz FREQ MODE RHP = 32I AVHP_ = +3dB
0
f = 3000Hz f = 1000Hz f = 100Hz 0.01 0.02 0.03 0.04 0.05 OUTPUT POWER (W)
0
0.01
0.02
0.03
0.04
0.05
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE)
MAX98088 toc86
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE)
MAX98088 toc87
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE)
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 f = 6000Hz f = 1000Hz f = 100Hz 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 OUTPUT POWER (W) MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 16I AVHP_ = +3dB
MAX98088 toc88
0 -10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 0
THD+N RATIO (dB)
MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I AVHP_ = +3dB
0 -10 -20 -30 -40 -50 -60 -70
MCLK = 12.288MHz LRCLK = 96kHz NI MODE RHP = 32I AVHP_ = +3dB
0
f = 6000Hz f = 1000Hz f = 100Hz 0.01 0.02 0.03 0.04 0.05 OUTPUT POWER (W)
f = 6000Hz f = 1000Hz f = 100Hz 0 0.01 0.02 0.03 0.04 0.05 OUTPUT POWER (W)
-80 -90
-90
44
Stereo Audio Codec with FLEXSOUND Technology
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
MAX98088
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE)
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 0 0.01 0.02 0.03 0.04 0.05 OUTPUT POWER (W) f = 1000Hz f = 100Hz MCLK = 12.288MHz LRCLK = 48kHz 256 Fs MODE LOW POWER MODE RHP = 16I AVHP_ = +3dB f = 6000Hz
MAX98088 toc89
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE)
MAX98088 toc90
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO HEADPHONE)
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 POUT = 0.01W POUT = 0.02W 10 100 1000 FREQUENCY (Hz) 10,000 100,000 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I AVHP_ = +3dB
MAX98088 toc91
0
0 -10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 10 100 POUT = 0.01W POUT = 0.02W 1000 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RHP = 32I AVHP_ = +3dB
0
10,000
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO HEADPHONE)
MAX98088 toc92
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO HEADPHONE)
MAX98088 toc93
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO HEADPHONE)
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 POUT = 0.01W POUT = 0.02W 10 100 1000 FREQUENCY (Hz) 10,000 100,000 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 16I AVHP_ = +3dB
MAX98088 toc94
0 -10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 10
THD+N RATIO (dB)
MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I AVHP_ = +3dB
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10
MCLK = 12.288MHz LRCLK = 96kHz NI MODE RHP = 32I AVHP_ = +3dB
0
POUT = 0.02W
POUT = 0.02W
POUT = 0.01W 100 1000 FREQUENCY (Hz) 10,000 100,000
POUT = 0.01W 100 1000 FREQUENCY (Hz) 10,000 100,000
-80 -90
45
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
GAIN vs. FREQUENCY (DAC TO HEADPHONE)
MAX98088 toc95
PVDD CURRENT vs. OUTPUT POWER (DAC TO HEADPHONE)
120 100 IPVDD (mA)
0 NORMALIZED GAIN (dBrA) -10 -20 -30 -40 -50 -60 -70 -80 10 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RHP = 32I 100 1000 FREQUENCY (Hz)
MODE = 1 MODE = 0
MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I
80 60 40 20
RPH = 16I
RPH = 32I
0 10,000 100,000 0.01 0.1 1 10 100 OUTPUT POWER PER CHANNEL (W)
PVDD CURRENT vs. OUTPUT POWER (DAC TO HEADPHONE)
MAX98088 toc97
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO HEADPHONE)
MAX98088 toc98
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO HEADPHONE)
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100
90 80 70 IPVDD (mA) 60 50 40 30 20 10 0
MCLK = 12.288MHz LRCLK = 48kHz LOW POWER MODE AVHP_ = +3dB
-10 -20 -30 PSRR (dB) -50 -60 -70 -80 -90 -40
VRIPPLE = 200mVP-P
VRIPPLE = 200mVP-P LOW POWER MODE
RIPPLE ON AVDD, DVDD, HPVDD RIPPLE ON SPKLVDD, SPKRVDD
RPH = 16I
PSRR (dB)
RIPPLE ON AVDD, DVDD, HPVDD
RIPPLE ON SPKLVDD, SPKRVDD
RPH = 32I
0.01 0.1 1 10 100
-100 10 100 1000 FREQUENCY (Hz) 10,000 100,000
10
100
1000 FREQUENCY (Hz)
10,000
100,000
OUTPUT POWER PER CHANNEL (mW)
46
MAX98088 toc99
100
0
0
MAX98088 toc96
10
140
Stereo Audio Codec with FLEXSOUND Technology
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
MAX98088
CROSSTALK vs. FREQUENCY (DAC TO HEADPHONE)
-10 -20 CROSSTALK (dB) -30 -40 -50 -60 -70 -80 -90 -100 10 100 1000 FREQUENCY (Hz) 10,000 100,000
SOFTWARE TURN-ON/OFF RESPONSE (DAC TO HEADPHONE, VSEN = 0)
MAX98088 toc101 MAX98088 toc100
0
MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I
SCL 1V/div
RIGHT TO LEFT
HEADPHONE OUTPUT 1V/div
LEFT TO RIGHT
10ms/div
SOFTWARE TURN-ON/OFF RESPONSE (DAC TO HEADPHONE, VSEN = 1)
MAX98088 toc102
SCL 1V/div
HEADPHONE OUTPUT 1V/div
10ms/div
47
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
FFT, 0dBFS (DAC TO HEADPHONE)
MAX98088 toc103
FFT, -60dBFS (DAC TO HEADPHONE)
MAX98088 toc104
FFT, 0dBFS (DAC TO HEADPHONE)
0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120
0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140 0 5000 10,000
AMPLITUDE (dBV)
MCLK = 13MHz LRCLK = 8kHz FREQ MODE RHP = 32I
-20 -40 -60 -80 -100 -120 -140
MCLK = 13MHz LRCLK = 8kHz FREQ MODE RHP = 32I
MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I
15,000
20,000
0
5000
10,000 FREQUENCY (Hz)
15,000
20,000
-140 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000
FREQUENCY (kHz)
FFT, -60dBFS (DAC TO HEADPHONE)
MAX98088 toc106
FFT, 0dBFS (DAC TO HEADPHONE)
0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140
-20 -40 AMPLITUDE (dBV) -60 -80 -100 -120 -140 -160 0 5000 10,000
MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I
MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I
15,000
20,000
0
5000
10,000 FREQUENCY (Hz)
15,000
20,000
FREQUENCY (Hz)
48
MAX98088 toc107
0
20
MAX98088 toc105
20
0
20
Stereo Audio Codec with FLEXSOUND Technology
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
MAX98088
FFT, -60dBFS (DAC TO HEADPHONE)
MAX98088 toc108
FFT, 0dBFS (DAC TO HEADPHONE)
0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120
-20 -40 AMPLITUDE (dBV) -60 -80 -100 -120 -140 -160 0 5000
MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I
MCLK = 12.288MHz LRCLK = 96kHz NI MODE RHP = 32I
10,000 FREQUENCY (Hz)
15,000
20,000
-140 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000
FFT, -60dBFS (DAC TO HEADPHONE)
MAX98088 toc110
FFT, -60dBFS (DAC TO HEADPHONE)
-20 -40 AMPLITUDE (dBV) -60 -80 -100 -120 -140
-20 -40 AMPLITUDE (dBV) -60 -80 -100 -120 -140 -160 0 5000
MCLK = 12.288MHz LRCLK = 96kHz NI MODE RHP = 32I
MCLK = 12.288MHz LRCLK = 48kHz LOW POWER MODE RHP = 32I
10,000 FREQUENCY (Hz)
15,000
20,000
-160 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000
MAX98088 toc111
0
0
MAX98088 toc109
0
20
49
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
FFT, -60dBFS (DAC TO HEADPHONE)
MAX98088 toc112
WIDEBAND FFT 0BFS (DAC TO HEADPHONE)
MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I
MAX98088 toc113
0 -20 AMPLITUDE (dBV) -40 -60 -80 -100 -120 -140 0 5000 10,000 FREQUENCY (kHz) 15,000
0 -20 OUTPUT AMPLITUDE (dBV) -40 -60 -80 -100 -120
MCLK = 12.288MHz LRCLK = 48kHz LOW POWER MODE RHP = 32I
20,000
0
1
10
100
1000
10,000
FREQUENCY (kHz)
WIDEBAND FFT -60dBFS (DAC TO HEADPHONE)
MAX98088 toc114
WIDEBAND FFT 0BFS (DAC TO HEADPHONE)
MAX98088 toc115
WIDEBAND FFT -60dBFS (DAC TO HEADPHONE)
MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I LOW POWER MODE
MAX98088 toc116
0 -20 OUTPUT AMPLITUDE (dBV) -40 -60 -80 -100 -120 0.1 1 10 100 1000
0 -20 OUTPUT AMPLITUDE (dBV) -40 -60 -80 -100 -120
OFF-ISOLATION (dB)
MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I
0 -20 -40 -60 -80 -100 -120 0.1 1 10 100 1000
MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I LOW POWER MODE
10,000
0
1
10
100
1000
10,000
10,000
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
50
Stereo Audio Codec with FLEXSOUND Technology
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.)
MAX98088
Line to Headphone
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (LINE TO HEADPHONE)
MAX98088 toc117
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO HEADPHONE)
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90
-10 -20 THD+N RATIO (dB) -30 -40 -50 -60 -70 -80 -90 0
RHP = 32I AVHP_ = +3dB CIN = 1F
RHP = 32I AVHP_ = +3dB CIN = 1F
f = 100Hz
f = 6000Hz
POUT = 0.020W
f = 1000Hz
0.01 0.02 0.03 0.04 0.05 OUTPUT POWER (W)
POUT = 0.01W
10 100 1000 FREQUENCY (Hz) 10,000 100,000
GAIN vs. FREQUENCY (LINE TO HEADPHONE)
MAX98088 toc119
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (LINE TO HEADPHONE)
MAX98088 toc120
CROSSTALK vs. FREQUENCY (LINE TO HEADPHONES)
-10 -20 CROSSTALK (dB) -30 -40 -50 -60 -70 -80
4 3 NORMALIZED GAIN (dB) 2
RHP = 32I CIN = 1F
-10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 10
VRIPPLE = 200mVP-P
RHP = 32I
1 0 -1 -2 -3 -4 -5 10 100 1000 FREQUENCY (Hz) 10,000 100,000
RIPPLE ON AVDD, DVDD, HPVDD
RIPPLE ON SPKLVDD, SPKRVDD
100
1000 FREQUENCY (Hz)
10,000
100,000
10
100
1000 FREQUENCY (Hz)
10,000
100,000
MAX98088 toc121
5
0
0
MAX98088 toc118
0
0
51
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Typical Operating Characteristics (continued)
(VAVDD = VPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to HPGND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CREG = 1FF, CC1N-C1P = 1FF, CHPVDD = CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) (Note 1)
Speaker Bypass Switch
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER BYPASS SWITCH)
-10 -20 THD+N (dB) -30 -40 -50 -60 -70 -80 10 100 1000 FREQUENCY (Hz) 10,000 100,000 0 0.05 0.10 0.15 0.20 0.25 OUTPUT POWER (W)
COMMON-MODE REJECTION RATIO vs. FREQUENCY (LINE TO HEADPHONES)
MAX98088 toc122
90 80 70 CMRR (dB) 60 50 40 30 20 10 0
AVPREGAIN = 20dB
RECEIVER AMPLIFIER DRIVING LOUDSPEAKER ZSPK = 8I + 68H
AVPREGAIN = 0dB
f = 1000kHz
f = 6000Hz
VOUT = -6dBV CIN = 1F RHP = 32I
f = 100Hz
ON-RESISTANCE vs. VCOM (SPEAKER BYPASS SWITCH)
MAX98088 toc124
OFF-ISOLATION vs. FREQUENCY (SPEAKER BYPASS SWITCH)
SPEAKER AMP DRIVING LOUDSPEAKER SPEAKER BYPASS SWITCH OPEN MEASURED AT RXIN_
MAX98088 toc125
4.0 3.5 3.0 RON (I) 2.5 2.0 1.5 1.0 0.5 0 0
ISW = 20mA
VSPK_VDD = 3.0V
0 -20 OFF-ISOLATION (dB) -40 -60 -80
VSPK_VDD = 3.7V
VSPK_VDD = 5.0V
50I LOAD ON RXIN_
VSPK_VDD = 4.2V
RECEIVER AMP DRIVING RXIN_
-100 -120 10 100 1000 FREQUENCY (Hz) 10,000 100,000
1
2
3 VCOM (V)
4
5
6
52
MAX98088 toc123
100
0
Stereo Audio Codec with FLEXSOUND Technology
Pin Configuration
MAX98088
TOP VIEW (BUMP SIDE DOWN)
1 2 3 4 5 6 7 8 9
A
SPKRN
SPKRGND
SPKLVDD
SPKLP
SPKLN
RECP/ LOUTL/ RXINP
PVDD
HPVSS
HPGND
B
SPKRN
SPKRGND
SPKLVDD
SPKLP
SPKLN
RECN/ LOUTR/ RXINN
C1P
C1N
HPVDD
C
SPKRP
SPKRP
SPKRVDD
SPKLGND
SPKLGND
N.C
N.C.
HPSNS
HPL
MAX98088 D
BCLKS1 SDOUTS1 SPKRVDD LRCLKS1 N.C. N.C. N.C. INB2 HPR
E
DVDDS1
MCLK
N.C.
SDINS1
IRQ
JACKSNS
INB1
MIC1P/
DIGMICDATA
INA2/ EXTMICN
F
DGND
BCLKS2
LRCLKS2
SDA
SCL
REG
MICBIAS
MIC1N/
DIGMICCLK
INA1/ EXTMICP
G
SDOUTS2
DVDDS2
SDINS2
DVDD
AVDD
REF
AGND
MIC2N
MIC2P
53
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Pin Description
PIN A1, B1 A2, B2 A3, B3 A4, B4 A5, B5 A6 A7 A8 A9 B6 B7 B8 B9 C1, C2 C3, D3 C4, C5 C6, C7, D5, D6, D7, E3 C8 C9 D1 D2 D4 D8 D9 E1 E2 E4 NAME SPKRN SPKRGND SPKLVDD SPKLP SPKLN RECP/LOUTL/ RXINP PVDD HPVSS HPGND RECN/LOUTR/ RXINN C1P C1N HPVDD SPKRP SPKRVDD SPKLGND N.C. HPSNS HPL BCLKS1 SDOUTS1 LRCLKS1 INB2 HPR DVDDS1 MCLK SDINS1 Right-Speaker Ground Left-Speaker, REF, Receiver Amp Power Supply. Bypass to SPKLGND with a 1FF and a 10FF capacitor. Positive Left-Channel Class D Speaker Output Negative Left-Channel Class D Speaker Output Positive Receiver Amplifier Output or Left Line Output. Can be positive bypass switch input when receiver amp is shut down. Headphone Power Supply. Bypass to HPGND with a 1FF capacitor. Inverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capacitor. Headphone Ground Negative Receiver Amplifier Output or Right Line Output. Can be negative bypass switch input when receiver amp is shut down. Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF ceramic capacitor between C1N and C1P. Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF ceramic capacitor between C1N and C1P. Noninverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capacitor. Positive Right-Channel Class D Speaker Output Right-Speaker Power Supply. Bypass to SPKRGND with a 1FF capacitor. Left-Speaker Ground No Connection Headphone Amplifier Ground Sense. Connect to the headphone jack ground terminal or connect to ground. Left-Channel Headphone Output S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the ICs are in slave mode and an output when in master mode. The input/output voltage is referenced to DVDDS1. S1 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS1. S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample rate clock and determines whether S1 audio data is routed to the left or right channel. In TDM mode, LRCLKS1 is a frame sync pulse. LRCLKS1 is an input when the IC is in slave mode and an output when in master mode. Single-Ended Line Input B2. Also positive differential line input B. Right-Channel Headphone Output S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor. Master Clock Input. Acceptable input frequency range is 10MHz to 60MHz. S1 Digital Audio Serial-Data DAC Input. The input/output voltage is referenced to DVDDS1. The input voltage is referenced to DVDDS1. FUNCTION Negative Right-Channel Class D Speaker Output
54
Stereo Audio Codec with FLEXSOUND Technology
Pin Description (continued)
PIN E5 E6 E7 E8 E9 F1 F2 NAME FUNCTION Hardware Interrupt Output. IRQ can be programmed to pull low when bits in status register 0x00 change state. Read status register 0x00 to clear IRQ once set. Repeat faults have no effect on IRQ until it is cleared by reading the I2C status register 0x00. Connect a 10kI pullup resistor to DVDD for full output swing. Jack Sense. Detects the insertion of a jack. See the Jack Detection section. Single-Ended Line Input B1. Also negative differential line input B. Positive Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can be retasked as a digital microphone data input. Single-Ended Line Input A2. Also positive differential line input A or negative differential external microphone input. Digital Ground S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the IC is in slave mode and an output when in master mode. The input/output voltage is referenced to DVDDS2. S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample rate clock and determines whether audio data on S2 is routed to the left or right channel. In TDM mode, LRCLKS2 is a frame sync pulse. LRCLKS2 is an input when the IC is in slave mode and an output when in master mode. The input/output voltage is referenced to DVDDS2. I2C Serial-Data Input/Output. Connect a pullup resistor to DVDD for full output swing. I2C Serial-Clock Input. Connect a pullup resistor to DVDD for full output swing. Common-Mode Voltage Reference. Bypass to AGND with a 1FF capacitor. Low-Noise Bias Voltage. Outputs a 2.2V microphone bias. An external resistor in the 2.2kI to 1kI range should be used to set the microphone current. Negative Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can be retasked as a digital microphone clock output. Single-Ended Line Input A1. Also negative differential line input A or positive differential external microphone input. S2 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS2. S2 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor. S2 Digital Audio Serial-Data DAC Input. The input voltage is referenced to DVDDS2. Digital Power Supply. Supply for the digital core and I2C interface. Bypass to DGND with a 1FF capacitor. Analog Power Supply. Bypass to AGND with a 1FF capacitor. Converter Reference. Bypass to AGND with a 2.2FF capacitor. Analog Ground Negative Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor. Positive Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor.
MAX98088
IRQ JACKSNS INB1 MIC1P/ DIGMICDATA INA2/ EXTMICN DGND BCLKS2
F3 F4 F5 F6 F7 F8 F9 G1 G2 G3 G4 G5 G6 G7 G8 G9
LRCLKS2 SDA SCL REG MICBIAS MIC1N/ DIGMICCLK INA1/ EXTMICP SDOUTS2 DVDDS2 SDINS2 DVDD AVDD REF AGND MIC2N MIC2P
55
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Detailed Description
The MAX98088 is a fully integrated stereo audio codec with FLEXSOUND technology and integrated amplifiers. Two differential microphone amplifiers can accept signals from three analog inputs. One input can be retasked to support two digital microphones. Any combination of two microphones (analog or digital) can be recorded simultaneously. The analog signals are amplified up to 50dB and recorded by the stereo ADC. The digital record path supports voice filtering with selectable preset highpass filters and high stopband attenuation at fS/2. An automatic gain control (AGC) circuit monitors the digitized signal and automatically adjusts the analog microphone gain to make best use of the ADC's dynamic range. A noise gate attenuates signals below the user-defined threshold to minimize the noise output by the ADC. The IC includes two analog line inputs. One of the line inputs can be optionally retasked as a third analog microphone input. Both line inputs support either stereo singleended input signals or mono differential signals. The line inputs are preamplified and then routed either to the ADC for recording or to the output amplifiers for playback. The single-ended line inputs signals from INA1 and INA2 can bypass the PGAs, and be connected directly to the ADC input to provide the best dynamic range. Integrated analog switches allow two differential microphone signals to be routed out the third microphone input to an external device. This eliminates the need for an external analog switch in systems that have two devices recording signals from the same microphone. Through two digital audio interfaces, the device can transmit one stereo audio signal and receive two stereo audio signals in a wide range of formats including I2S, PCM, and up to four mono slots in TDM. Each interface can be connected to either of two audio ports (S1 and S2) for communication with external devices. Both audio interfaces support 8kHz to 96kHz sample rates. Each input signal is independently equalized using 5-band parametric equalizers. A multiband automatic level control (ALC) boosts signals by up to 12dB. One signal path additionally supports the same voiceband filtering as the ADC path. The IC includes a stereo Class D speaker amplifier, a high-efficiency Class H stereo headphone amplifiers, and a differential receiver amplifier that can be configured as a stereo line output. When the receiver amplifier is disabled, analog switches allow RECP/RXINP and RECN/RXINN to be reused for signal routing. In systems where a single transducer is used for both the loudspeaker and receiver, an external receiver amplifier can be routed to the left speaker through RECP/RXINP and RECN/RXINN, bypassing the Class D amplifier, to connect to the loudspeaker. If the internal receiver amplifier is used, then leave RECP/ RXINP and RECN/RXINN unconnected. In systems where an external amplifier drives both the receiver and the MAX98088/MAX98089's input, one of the differential signals can be disconnected from the receiver when not needed by passing it through the analog switch that connects RECP/RXINP to RECN/RXINN. The stereo Class D amplifier provides efficient amplification for two speakers. The amplifier includes active emissions limiting to minimize the radiated emissions (EMI) traditionally associated with Class D. In most systems, no output filtering is required to meet standard EMI limits. To optimize speaker sound quality, the IC includes an excursion limiter, a distortion limiter, and a power limiter. The excursion limiter is a dynamic highpass filter with variable corner frequency that increases in response to high signal levels. Low-frequency energy typically causes more distortion than useful sound at high signal levels, so attenuating low frequencies allows the speaker to play louder without distortion or damage. At lower signal levels, the filter corner frequency reduces to pass more low frequency energy when the speaker can handle it. The distortion limiter reduces the volume when the output signal exceeds a preset distortion level. This ensures that regardless of input signal and battery voltage, excessive distortion is never heard by the user. The power limiter monitors the continuous power into the loudspeaker and lowers the signal level if the speaker is at risk of overheating. The stereo Class H headphone amplifier uses a dualmode charge pump to maximize efficiency while outputting a ground-referenced signal. This eliminates the need for DC-blocking capacitors or a midrail bias for the headphone jack ground return. Ground sense reduces output noise caused by ground return current. The IC integrates jack detection allowing the detection of insertion and removal of accessories.
56
Stereo Audio Codec with FLEXSOUND Technology
Configure the MAX98088 using the I2C control bus. The IC uses a slave address of 0x20 or 00100000 for write operations and 0x21 or 00100001 for read operations. See the I2C Serial Interface section for a complete interface description.
I2C Slave Address
Table 1 lists all of the registers, their addresses, and power-on-reset states. Registers 0x00 to 0x03 and 0xFF are read-only while all of the other registers are read/ write. Write zeros to all unused bits in the register table when updating the register, unless otherwise noted.
Registers
MAX98088
Table 1. Register Map
REGISTER STATUS Status Microphone AGC/NG Jack Status Battery Voltage Interrupt Enable Master Clock Clock Mode Any Clock Control Format Clock I/O Configuration Time-Division Multiplex Filters Clock Mode Any Clock Control Format Clock I/O Configuration PLL2 NI2[7:1] MAS2 0 SEL2 WCI2 0 BCI2 DAC_ ORS2 0 DLY2 0 LBEN2 0 0 TDM2 FSW2 BSEL2 PLL1 NI1[7:1] MAS1 WCI1 BCI1 DAC_ORS1 LTEN1 DLY1 0 LBEN1 0 0 TDM1 FSW1 BSEL1 -- -- ICLD B7 CLD B6 SLD NG JKSNS -- ISLD -- -- IULK 0 0 -- -- B5 ULK B4 -- B3 -- B2 -- AGC -- VBAT 0 IJDET 0 -- -- B1 JDET B0 -- ADDRESS DEFAULT R/W PAGE 0x00 0x01 0x02 0x03 0x0F -- -- -- -- 0x00 R R R R/W R/W 111 70 110 110 111
MASTER CLOCK CONTROL 0 0 SR1 NI1[14:8] NI1[0] WS1 PSCLK 0 0 FREQ1 0 0 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0 NI2[0] WS2 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 R/W 81 DAI1 CLOCK CONTROL R/W 81, 82 R/W R/W R/W R/W 82 82 76 77
DAI1 CONFIGURATION ADC_OSR1 SEL1 SLOTL1 MODE1
DMONO1 HIZOFF1 SDOEN1 SDIEN1 SLOTDLY1 DHF1 0 NI2[14:8] 0 DVFLT1 0
R/W 77, 78 R/W R/W R/W R/W R/W R/W R/W 78 86 81 82 82 76 77
SLOTR1 AVFLT1 SR2
DAI2 CLOCK CONTROL
DAI2 CONFIGURATION
DMONO2 HIZOFF2 SDOEN2 SDIEN2
R/W 77, 78
57
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 1. Register Map (continued)
REGISTER Time-Division Multiplex Filters SRC Sample Rate Converter MIXERS DAC Mixer Left ADC Mixer Right ADC Mixer Left Headphone Amplifier Mixer Right Headphone Amplifier Mixer Headphone Amplifier Mixer Control Left Receiver Amplifier Mixer Right Receiver Amplifier Mixer Receiver LINE_ Amplifier MODE Mixer Control Left Speaker Amplifier Mixer Right Speaker Amplifier Mixer Speaker Amplifier Mixer Control 0 0 0 0 0 0 0 0 0 MIXDAL MIXADL MIXADR MIXDAR 0x22 0x23 0x24 0x00 0x00 0x00 R/W R/W R/W 92 69 69 B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W PAGE 0x1F DCB2 SRC_ ENR 0x20 0x21 0x00 0x00 0x00 R/W R/W R/W 78 86 85 SLOTL2 0 0 0 0 0 0 SLOTR2 0 SRMIX_ MODE DHF2 SRMIX_ ENL SLOTDLY2 0 SRMIX_ ENR 0 SRC_ ENL
MIXHPL
0x25
0x00
R/W
105
MIXHPR
0x26
0x00
R/W
105
MIXHPR_ MIXHPL_ PATHSEL PATHSEL
MIXHPR_GAIN
MIXHPL_GAIN
0x27
0x00
R/W
105
MIXRECL
0x28
0x00
R/W
94
MIXRECR
0x29
0x00
R/W
94
MIXRECR_GAIN
MIXRECL_GAIN
0x2A
0x00
R/W
94
MIXSPL
0x2B
0x00
R/W
97
MIXSPR
0x2C
0x00
R/W
97
MIXSPR_GAIN
MIXSPL_GAIN
0x2D
0x00
R/W
97
58
Stereo Audio Codec with FLEXSOUND Technology
Table 1. Register Map (continued)
REGISTER Sidetone DAI1 Playback Level DAI1 Playback Level DAI2 Playback Level DAI2 Playback Level Left ADC Level Right ADC Level Microphone 1 Input Level Microphone 2 Input Level INA Input Level INB Input Level Left Headphone Amplifier Volume Control Right Headphone Amplifier Volume Control B7 DSTS DV1M 0 B6 B5 0 DV1G B4 B3 B2 DVST DV1 B1 B0 ADDRESS DEFAULT R/W PAGE 0x2E 0x2F 0x00 0x00 R/W R/W 74 91 LEVEL CONTROL
MAX98088
0
0
0
EQCLP1
DVEQ1
0x30
0x00
R/W
90
DV2M
0
0
0
DV2
0x31
0x00
R/W
91
0 0 0 0 0 0 0
0 0 0 PA1EN PA2EN INAEXT INBEXT
0
EQCLP2 AVLG AVRG
DVEQ2 AVL AVR PGAM1 PGAM2
0x32 0x33 0x34 0x35 0x36
0x00 0x00 0x00 0x00 0x00 0x00 0x00
R/W R/W R/W R/W R/W R/W R/W
90 73 73 66 66 68 68
0 0
0 0
0 0
PGAINA PGAINB
0x37 0x38
HPLM
0
0
HPVOLL
0x39
0x00
R/W
106
HPRM
0
0
HPVOLR
0x3A
0x00
R/W
106
Left Receiver Amplifier RECLM Volume Control Right Receiver Amplifier Volume Control
0
0
RECVOLL
0x3B
0x00
R/W
95
RECRM
0
0
RECVOLR
0x3C
0x00
R/W
95
59
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 1. Register Map (continued)
REGISTER Left Speaker Amplifier Volume Control Right Speaker Amplifier Volume Control B7 SPLM B6 0 B5 0 B4 B3 B2 SPVOLL B1 B0 ADDRESS DEFAULT R/W PAGE 0x3D 0x00 R/W 98
SPRM
0
0
SPVOLR
0x3E
0x00
R/W
98
MICROPHONE AGC Configuration AGCSRC Threshold Excursion Limiter Filter Excursion Limiter Threshold ALC Power Limiter Power Limiter Distortion Limiter CONFIGURATION Audio Input Microphone INADIFF INBDIFF MICCLK VSEN 0 0 0 ZDEN 0 0 0 0 MIC2BYP 0 0 0 0 0 0 0 0 0 0 0 0 EXTMIC EQ2EN EQ1EN 0 0x47 0x48 0x49 0x4A 0x4B 0x00 0x00 0x00 0x00 0x00 R/W R/W 68 66 67, 107 110 DIGMICL DIGMICR AGCRLS ANTH AGCATK AGCTH AGCHLD 0x3F 0x40 0x00 0x00 R/W 70, 71 R/W 71
SPEAKER SIGNAL PROCESSING 0 0 ALCEN 0 DHPUCF 0 ALCRLS PWRTH PWRT2 THDCLP 0 0 0 0 0 ALCMB 0 0 DHPLCF DHPTH ALCTH PWRK PWRT1 0 THDT1 0x41 0x42 0x43 0x44 0x45 0x46 0x00 0x00 0x00 0x00 0x00 0x00 R/W R/W 100 100
R/W 89, 100 R/W R/W R/W 101 102 103
Level Control VS2EN Bypass INABYP Switches Jack Detection Input Enable Output Enable Top-Level Bias Control DAC Low Power Mode 1 DAC Low Power Mode 2 System Shutdown 60 0 SHDN JDETEN
R/W 90, 108 R/W R/W
RECBYP SPKBYP JDEB
POWER MANAGEMENT INAEN HPLEN INBEN HPREN 0 SPLEN 0 SPREN BIASEN MBEN 0 ADLEN ADREN DAREN 0 0x4C 0x4D 0x4E 0x4F 0x00 0x00 0xF0 0x00 R/W R/W R/W R/W 63 64 64 83
RECLEN RECREN DALEN 0 0 0
BGEN SPREGEN VCMEN DAI2_DAC_LP
DAI1_DAC_LP DAC2_IP_ DAC1_IP_ CGM2_ CGM1_ DITH_EN DITH_EN EN EN PERFMODE HPPLYBACK PWRSV8K PWRSV
0 VBATEN
0 0
0 0
0x50 0x51
0x0F 0x00
R/W R/W
83 63, 100
Stereo Audio Codec with FLEXSOUND Technology
Table 1. Register Map (continued)
REGISTER B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W PAGE 0x52/0x84 0x53/0x85 0x54/0x86 0x55/0x87 0x56/0x88 0x57/0x89 0x58/0x8A 0x59/0x8B 0x5A/0x8C 0x5B/0x8D 0x5C/0x8E 0x5D/0x8F 0x5E/0x90 0x5F/0x91 0x60/0x92 0x61/0x93 0x62/0x94 0x63/0x95 0x64/0x96 0x65/0x97 0x66/0x98 0x67/0x99 0x68/0x9A 0x69/0x9B 0x6A/0x9C 0x6B/0x9D 0x6C/0x9E 0x6D/0x9F 0x6E/0xAE 0x6F/0xA1 0x70/0xA2 0x71/0xA3 0x72/0xA4 0x73/0xA5 0x74/0xA6 0x75/0xA7 0x76/0xA8 0x77/0xA9 0x78/0xAA 0x79/0xAB 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 DSP COEFFICIENTS K_1[15:8] K_1[7:0] K1_1[15:8] K1_1[7:0] EQ Band 1 (DAI1/DAI2) K2_1[15:8] K2_1[7:0] c1_1[15:8] c1_1[7:0] c2_1[15:8] c2_1[7:0] K_2[15:8] K_2[7:0] K1_2[15:8] K1_2[7:0] EQ Band 2 (DAI1/DAI2) K2_2[15:8] K2_2[7:0] c1_2[15:8] c1_2[7:0] c2_2[15:8] c2_2[7:0] K_3[15:8] K_3[7:0] K1_3[15:8] K1_3[7:0] EQ Band 3 (DAI1/DAI2) K2_3[15:8] K2_3[7:0] c1_3[15:8] c1_3[7:0] c2_3[15:8] c2_3[7:0] K_4[15:8] K_4[7:0] K1_4[15:8] K1_4[7:0] EQ Band 4 (DAI1/DAI2) K2_4[15:8] K2_4[7:0] c1_4[15:8] c1_4[7:0] c2_4[15:8] c2_4[7:0]
MAX98088
61
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 1. Register Map (continued)
REGISTER B7 B6 B5 B4 B3 K_5[7:0] K1_5[15:8] K1_5[7:0] EQ Band 5 (DAI1/DAI2) K2_5[15:8] K2_5[7:0] c1_5[15:8] c1_5[7:0] c2_5[15:8] c2_5[7:0] a1[15:8] a1[7:0] a2[15:8] Excursion Limiter Biquad (DAI1/DAI2) a2[7:0] b0[15:8] b0[7:0] b1[15:8] b1[7:0] b2[15:8] b2[7:0] REVISION ID Rev ID REV 0xFF 0x40 R 112 B2 B1 B0 ADDRESS DEFAULT R/W PAGE 0x7A/0xAC 0x7B/0xAD 0x7C/0xAE 0x7D/0xAF 0x7E/0xB0 0x7F/0xB1 0x80/0xB2 0x81/0xB3 0x82/0xB4 0x83/0xB5 0xB6/0xC0 0xB7/0xC1 0xB8/0xC2 0xB9/0xC3 0xBA/0xC4 0xBB/0xC5 0xBC/0xC6 0xBD/0xC7 0xBE/0xC8 0xBF/0xC9 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX 0xXX R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 89 K_5[15:8]
62
Stereo Audio Codec with FLEXSOUND Technology
The IC includes comprehensive power management to allow the disabling of all unused circuits, minimizing supply current.
Power Management
MAX98088
Table 2. Power Management Registers
REGISTER BIT 7 6 3 NAME DESCRIPTION Global Shutdown. Disables everything except the headset detection circuitry, which is controlled separately. 0 = Device Shutdown 1 = Device Enabled See the Battery Measurement section. Performance Mode. Selects DAC to headphone playback performance mode. 0 = High performance playback mode 1 = Low power playback mode.. Headphone Only Playback Mode. Configures System Bias Control register bits for low power playback when using DAC to headphone playback path only. When enabled, this bit overrides the System Bias Control register settings. When disabled, the System Bias Control register is used to enable system bias blocks. Set both HPPLYBCK and PERFMODE for lowest power consumption when using DAC to headphone playback path only. 0 = Disabled 1 = Enabled. 8kHz Power Save Mode. PWRSV8K configures the ADC for reduced power consumption when fS = 8kHz. PWRSV8K can be used in conjunction with PWRSV for more power savings. 0 = Normal, high-performance mode. 1 = Low power mode. Power Save Mode. PWRSV configures the ADC for reduced power consumption for all sample rates. PWRSV can be used in conjunction with PWRSV8K for more power savings. 0 = Normal, high-performance mode. 1 = Low power mode. Line Input A Enable 0 = Disabled 1 = Enabled Line Input B Enable 0 = Disabled 1 = Enabled Microphone Bias Enable 0 = Disabled 1 = Enabled Left ADC Enable 0 = Disabled 1 = Enabled Right ADC Enable 0 = Disabled 1 = Enabled
SHDN VBATEN PERFMODE
0x51
2
HPPLYBCK
1
PWRSV8K
0
PWRSV
7
INAEN
6
INBEN
0x4C
3
MBEN
1
ADLEN
0
ADREN
63
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 2. Power Management Registers (continued)
REGISTER BIT 7 NAME HPLEN Left Headphone Enable 0 = Disabled 1 = Enabled Right Headphone Enable 0 = Disabled 1 = Enabled Left Speaker Enable 0 = Disabled 1 = Enabled Right Speaker Enable 0 = Disabled 1 = Enabled Receiver/Left Line Output Enable. Use this bit to enable the differential receiver output or left line output. 0 = Disabled 1 = Enabled Right Line Output Enable. Use this bit to enable the right line output. 0 = Disabled 1 = Enabled Left DAC Enable 0 = Disabled 1 = Enabled Right DAC Enable 0 = Disabled 1 = Enabled Bandgap Enable 0 = Disabled 1 = Enabled 2.5V Regulator Enable. SPREGEN enables a 2.5V internal regulator required for the ADC, speaker and receiver amplifier. The 2.5V regulator is powered by SPKLVDD. 0 = Disabled 1 = Enabled Common-Mode Voltage Resistor String Enable. VCMEN enables the common mode voltages for the amplifiers in the CODEC. 0 = Disabled 1 = Enabled Chip Bias Enable. BIASEN needs to be set for the CODEC amplifiers to be enabled. 0 = Disabled 1 = Enabled DESCRIPTION
6
HPREN
5
SPLEN
4 0x4D 3
SPREN
RECLEN
2
RECREN
1
DALEN
0
DAREN
7
BGEN
6 0x4E 5
SPREGEN
VCMEN
4
BIASEN
64
Stereo Audio Codec with FLEXSOUND Technology
The device includes three differential microphone inputs and a low-noise microphone bias for powering the microphones (Figure 6). One microphone input can also be configured as a digital microphone input accepting signals from up to two digital microphones. Two microphones, analog or digital, can be recorded simultaneously.
Microphone Inputs
MIC2P/MIC2N and EXTMICP/EXTMICN. MIC1P/MIC1N then become outputs that route the microphone signals to an external device as needed. Two devices can then record microphone signals without needing external analog switches. Analog microphone signals are amplified by two stages of gain and then routed to the ADCs. The first stage offers selectable 0dB, 20dB, or 30dB settings. The second stage is a programmable-gain amplifier (PGA) adjustable from 0dB to 20dB in 1dB steps. To maximize the signalto-noise ratio, use the gain in the first stage whenever possible. Zero-crossing detection is included on the PGA to minimize zipper noise while making gain changes.
MAX98088
In the typical application, one microphone input is used for the handset microphone and the other is used as an accessory microphone. In systems using a background noise microphone, INA can be retasked as another microphone input. In systems where the codec is not the only device recording microphone signals, connect microphones to
MCLK MICBIAS MBEN MIC1P/ DIGMICDATA MIC1N/ DIGMICCLK EXTMIC MIC2BYP ADLEN ADCL PA1EN: 0/20/30dB REG
CLOCK CONTROL PGAM1: +20dB TO 0dB
MIC2P
MIX
MIC2N EXTMIC PA2EN: 0/20/30dB PGAM1: +20dB TO 0dB MIXADL
INABYP PGAINA: +20dB TO -6dB INA1/EXTMICP INADIFF MIXADR MIX ADCR ADREN
INA2/EXTMICN PGAINA: +20dB TO -6dB
Figure 6. Microphone Input Block Diagram 65
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 3. Microphone Input Registers
REGISTER BIT 6 PA1EN/PA2EN 5 4 NAME DESCRIPTION MIC1/MIC2 Preamplifier Gain Course microphone gain adjustment. 00 = Preamplifier disabled 01 = 0dB 10 = 20dB 11 = 30dB MIC1/MIC2 PGA Fine microphone gain adjustment. VALUE 3 0x35/0x36 2 0x00 0x01 0x02 PGAM1/PGAM2 0x03 0x04 0x05 1 0x06 0x07 0x08 0 0x09 GAIN (dB) +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 VALUE 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 to 0x1F GAIN (dB) +9 +8 +7 +6 +5 +4 +3 +2 +1 0
7 MICCLK 6
0x0A +10 Digital Microphone Clock Frequency Select a frequency that is within the digital microphone's clock frequency range. Set OSR1 = 1 when using a digital microphone. 00 = PCLK/8 01 = PCLK/6 10 = 64 x LRCLK 11 = Reserved Left Digital Microphone Enable Set PAL1EN = 00 for proper operation. 0 = Disabled 1 = Enabled Right Digital Microphone Enable Set PAR1EN = 00 for proper operation. 0 = Disabled 1 = Enabled External Microphone Connection Routes INA_/EXTMIC_ to the microphone preamplifiers. Set INAEN = 0 when using INA_/EXTMIC_ as a microphone input. 00 = Disabled 01 = MIC1 input 10 = MIC2 input 11 = Reserved
5 0x48 4
DIGMICL
DIGMICR
1 EXTMIC 0
66
Stereo Audio Codec with FLEXSOUND Technology
Table 3. Microphone Input Registers (continued)
REGISTER BIT 7 NAME INABYP DESCRIPTION INA_/EXTMIC_ to MIC1_ Bypass Switch 0 = Disabled 1 = Enabled MIC1_ to MIC2_ Bypass Switch 0 = Disabled 1 = Enabled
MAX98088
4 0x4A 1
MIC2BYP
RECBYP See the Output Bypass Switches section.
0
SPKBYP
The device includes two sets of line inputs (Figure 7). Each set can be configured as a stereo single-ended input or as a mono differential input. Each input includes adjustable gain to match a wide range of input signal levels. If a custom gain is needed, the external gain mode provides a trimmed feedback resistor. Set the gain
Line Inputs
by choosing the appropriate input resistor and using the following formula: AVPGAIN = 20 x log (20K/RIN) The external gain mode also allows summing multiple signals into a single input, by connecting multiple input resistors as show in Figure 8, and inputting signals larger than 1VP-P.
INABYP PGAINA: +20dB TO -6dB INADIFF PGAINA: +20dB TO -6dB
INA1/ EXTMICP
INA2/ EXTMICN
LEFT INPUT 1 LEFT INPUT 2 INA1/EXTMICP VCM
20kI
PGAINB: +20dB TO -6dB INB1 INBDIFF
RIGHT INPUT 1 RIGHT INPUT 2 INA2/EXTMICN
20kI
VCM
PGAINB: +20dB TO -6dB INB2
Figure 7. Line Input Block Diagram
Figure 8. Summing Multiple Input Signals into INA/INB
67
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 4. Line Input Registers
REGISTER BIT NAME DESCRIPTION Line Input A/B External Gain Switches out the internal input resistor and selects a trimmed 20kI feedback resistor. Use an external input resistor to set the gain of the line input. 0 = Disabled 1 = Enabled Line Input A/B Internal Gain Settings 000 = +20dB 001 = +14dB 010 = +3dB 011 = 0dB 100 = -3dB 101 = -6dB 110 = -6dB 111 = -6dB Line Input A Differential Enable 0 = Stereo single-ended input 1 = Mono differential input Line Input B Differential Enable 0 = Stereo single-ended input 1 = Mono differential input
6
INAEXT/INBEXT
0x37/0x38
2
1
PGAINA/PGAINB
0
7 0x47 6
INADIFF
INBDIFF
The IC's stereo ADC accepts input from the microphone amplifiers, line inputs amplifiers, and directly from the INA1 and INA2. The ADC mixer routes any combination of the eight audio inputs to the left and right ADCs (Figure 9).
ADC Input Mixers
PGAM1: +20dB TO 0dB
PA1EN: 0/20/30dB
MIX PGAM2: +20dB TO 0dB MIXADL
ADLEN ADCL
PA2EN: 0/20/30dB
MIX PGAINA: +20dB TO -6dB INADIFF MIXADR
ADCR ADREN
+
PGAINA: +20dB TO -6dB
PGAINB: +20dB TO -6dB INBDIFF
+
PGAINB: +20dB TO -6dB
Figure 9. ADC Input Mixer Block Diagram 68
Stereo Audio Codec with FLEXSOUND Technology
Table 5. ADC Input Mixer Register
REGISTER BIT 7 6 5 0x23/0x24 4 3 2 1 0 MIXADL/MIXADR NAME DESCRIPTION Left/Right ADC Input Mixer Selects which analog inputs are recorded by the left/right ADC. 1xxxxxxx = MIC1 x1xxxxxx = MIC2 xx1xxxxx = INA1 pin direct xxx1xxxx = INA2 pin direct xxxx1xxx = INA1 xxxxx1xx = INA2 (INADIFF = 0) or INA2 - INA1 (INADIFF = 1) xxxxxx1x = INB1 xxxxxxx1 = INB2 (INBDIFF = 0) or INB2 - INB1 (INBDIFF = 1)
MAX98088
The device's record signal path includes both automatic gain control (AGC) for the microphone inputs and a digital noise gate at the output of the ADC (Figure 10). Microphone AGC The IC's AGC monitors the signal level at the output of the ADC and then adjusts the MIC1 and MIC2 analog PGA settings automatically. When the signal level is below the predefined threshold, the gain is increased up to its maximum (20dB). If the signal exceeds the threshold, the gain is reduced to prevent the output signal level exceeding the threshold. When AGC is enabled, the microphone PGA is not user programmable. The AGC provides a more constant signal level and improves the available ADC dynamic range.
Record Path Signal Processing
Noise Gate Since the AGC increases the levels of all signals below a user-defined threshold, the noise floor is effectively increased by 20dB. To counteract this, the noise gate reduces the gain at low signal levels. Unlike typical noise gates that completely silence the output below a defined level, the noise gate in the IC applies downward expansion. The noise gate attenuates the output at a rate of 1dB for each 2dB the signal is below the threshold. The noise gate can be used in conjunction with the AGC or on its own. When the AGC is enabled, the noise gate reduces the output level only when the AGC has set the gain to the maximum setting. Figure 11 shows the gain response resulting from using the AGC and noise gate.
AGC AND NOISE GATE AMPLITUDE RESPONSE
PA1EN: 0/20/30dB
0
PGAM1: +20dB TO -6dB AUTOMATIC GAIN CONTROL MODE1 AVFLT NOISE GATE AUDIO/ VOICE FILTERS AVRG: 0/6/ 12/18dB AVR:0dB TO -15dB
AGC ONLY -20 OUTPUT AMPLITUDE (dBFS) AGC AND NOISE GATE -40 -60 -80 -100 -120 -120 -100 -80 -60 -40 -20 0 INPUT AMPLITUDE (dBFS) AGC AND NOISE GATE DISABLED NOISE GATE ONLY
PA2EN: 0/20/30dB
PGAM2: +20dB TO 0dB
MIX
ADCL ADLEN
AVLG: 0/6/ 12/18dB AVL:0dB TO -15dB
MIXADL
SRMIX_ MODE
SAMPLE RATE CONVERTER
MIX
ADCR ADREN
MIXADR
Figure 10. Record Path Signal Processing Block Diagram
Figure 11. AGC and Noise Gate Input vs. Output Gain 69
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 6. Record Path Signal Processing Registers
REGISTER BIT 7 NAME DESCRIPTION Noise Gate Attenuation Reports the current noise gate attenuation. 000 = 0dB 001 = 1dB 010 = 2dB 011 = 3dB to 5dB 100 = 6dB to 7dB 101 = 8dB to 9dB 110 = 10dB to 11dB 111 = 12dB AGC Gain Reports the current AGC gain setting. VALUE 0x00 3 0x01 0x02 2 AGC 0x03 0x04 0x05 0x06 1 0x07 0x08 0 0x09 0x0A GAIN (dB) +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 VALUE 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 to 0x1F GAIN (dB) +9 +8 +7 +6 +5 +4 +3 +2 +1 0
6
NG
5
4 0x01
7
AGCSRC
AGC/Noise Gate Signal Source Determines which ADC channel the AGC and noise gates analyze. Gain is adjusted on both channels regardless of the AGCSRC setting. 0 = Left ADC output 1 = Maximum of either the left or right ADC output AGC Release Time Defined as the duration from start to finish of gain increase in the region shown in Figure 12. Release times are longer for low AGC threshold levels. 000 = 78ms 001 = 156ms 010 = 312ms 011 = 625ms 100 = 1.25s 101 = 2.5s 110 = 5s 111 = 10s
6 0x3F 5 AGCRLS
4
70
Stereo Audio Codec with FLEXSOUND Technology
Table 6. Record Path Signal Processing Registers (continued)
REGISTER BIT 3 AGCATK 2 0x3F 1 AGCHLD 0 NAME DESCRIPTION AGC Attack Time Defined as the time required to reduce gain by 63% of the total gain reduction (one time constant of the exponential response). Attack times are longer for low AGC threshold levels. See Figure 12 for details. 00 = 2ms 01 = 7.2ms 10 = 31ms 11 = 123ms AGC Hold Time The delay before the AGC release begins. The hold time counter starts whenever the signal drops below the AGC threshold and is reset by any signal that exceeds the threshold. Set AGCHLD to enable the AGC circuit. See Figure 12 for details. 00 = AGC disabled 01 = 50ms 10 = 100ms 11 = 400ms Noise Gate Threshold Gain is reduced for signals below the threshold to quiet noise. The thresholds are relative to the ADC's full-scale output voltage. VALUE 6 ANTH 5 0x0 0x1 0x2 0x3 0x4 0x5 4 0x40 3 0x6 0x7 THRESHOLD (dBFS) Noise gate disabled Reserved Reserved -64 -62 -58 -53 -50 VALUE 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF THRESHOLD (dBFS) -45 -41 -38 -34 -30 -27 -22 -16
MAX98088
7
AGC Threshold Gain is reduced when signals exceed the threshold to prevent clipping. The thresholds are relative to the ADC's full-scale voltage. VALUE THRESHOLD (dBFS) -3 -4 -5 -6 -7 -8 -9 -10 VALUE 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF THRESHOLD (dBFS) -11 -12 -13 -14 -15 -16 -17 -18
2 AGCTH 1
0x0 0x1 0x2 0x3 0x4 0x5
0
0x6 0x7
71
Stereo Audio Codec with FLEXSOUND Technology MAX98088
ATTACK TIME
HOLD TIME
RELEASE TIME
Figure 12. AGC Timing
The IC includes separate digital level control for the left and right ADC outputs (Figure 13). To optimize dynamic
ADC Record Level Control
range, use analog gain to adjust the signal level and set the digital level control to 0dB whenever possible. Digital level control is primarily used when adjusting the record level for digital microphones.
NOISE GATE AUTOMATIC GAIN CONTROL AUDIO/ VOICE FILTERS AVRG: 0/6/ 12/18dB AVR:0dB TO -15dB SAMPLE RATE CONVERTER
MODE1 AVFLT
ADCL ADLEN
AVLG: 0/6/ 12/18dB AVL:0dB TO -15dB SRMIX_ MODE
ADCR ADREN
Figure 13. ADC Record Level Control Block Diagram
72
Stereo Audio Codec with FLEXSOUND Technology
Table 7. ADC Record Level Control Register
REGISTER BIT 5 AVLG/AVRG 4 3 0x33/0x34 2 AVL/AVR NAME Left/Right ADC Gain 00 = 0dB 01 = 6dB 10 = 12dB 11 = 18dB Left/Right ADC Level VALUE 0x0 0x1 0x2 0x3 0x4 0x5 0 0x6 0x7 GAIN (dB) +3 +2 +1 0 -1 -2 -3 -4 VALUE 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF GAIN (dB) -5 -6 -7 -8 -9 -10 -11 -12 DESCRIPTION
MAX98088
1
Enable sidetone during full-duplex operation to add a low-level copy of the recorded audio signal to the playback audio signal (Figure 14). Sidetone is commonly
Sidetone
used in telephony to allow the speaker to hear himself speak, providing a more natural user experience. The IC implements sidetone digitally. Doing so helps prevent unwanted feedback into the playback signal path and better matches the playback audio signal.
DVST: 0dB TO -60dB SIDETONE DSTS MIX
DV1G: 0/6/12/18dB
+
MULTI BAND ALC DVEQ1: 0dB TO -15dB DVEQ2: 0dB TO -15dB
AUTOMATIC GAIN CONTROL MODE1 AVFLT ADLEN ADCL AVLG: 0/6/ 12/18dB AVL:0dB TO -15dB SRMIX_ MODE
NOISE GATE AUDIO/ VOICE FILTERS
5-BAND PARAMETRIC EQ EQ1EN
5-BAND PARAMETRIC EQ EQ2EN MIX AUDIO/ FILTERS DCB2 MIXDAL DACL DALEN
EXCURSION LIMITER AVRG: 0/6/ 12/18dB AVR:0dB TO -15dB
DV2: 0dB TO -15dB
SAMPLE RATE CONVERTER
ADCR ADREN
DV1: 0dB TO -15dB
AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR DAREN
Figure 14. Sidetone Block Diagram 73
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 8. Sidetone Register
REGISTER BIT 7 DSTS 6 NAME DESCRIPTION Sidetone Source Selects which ADC output is fed back as sidetone. When mixing the left and right ADC outputs, each is attenuated by 6dB to prevent full-scale signals from clipping. 00 = Sidetone disabled 01 = Left ADC 10 = Right ADC 11 = Left + Right ADC Sidetone Level Adjusts the sidetone signal level. All levels are referenced to the ADC's full-scale output. VALUE 0x00 3 0x2E 0x01 0x02 0x03 0x04 2 0x05 DVST 0x06 0x07 0x08 1 0x09 0x0A 0x0B 0x0C 0 0x0D 0x0E 0x0F LEVEL (dB) Sidetone disabled -0.5 -2.5 -4.5 -6.5 -8.5 -10.5 -12.5 -14.5 -16.5 -18.5 -20.5 -22.5 -24.5 -26.5 -28.5 VALUE 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F LEVEL (dB) -30.5 -32.5 -34.5 -36.5 -38.5 -40.5 -42.5 -44.5 -46.5 -48.5 -50.5 -52.5 -54.5 -56.6 -58.5 -60.5
4
The IC includes two separate playback signal paths and one record signal path. Digital audio interface 1 (DAI1) is used to transmit the recorded stereo audio signal and receive a stereo audio signal for playback. Digital audio interface 2 (DAI2) is used to receive a second stereo audio signal. Use DAI1 for all full-duplex operations and for all voice signals. Use DAI2 for music and to mix two playback audio signals. The digital audio interfaces are separate from the audio ports to enable either interface to communicate with any external device connected to the audio ports. Each audio interface can be configured in a variety of formats including left justified, I2S, PCM, and time division multiplexed (TDM). TDM mode supports up to 4 mono audio slots in each frame. The IC can use up to
Digital Audio Interfaces
2 mono slots per interface, leaving the remaining two slots available for another device. Table 9 shows how to configure the device for common digital audio formats. Figures 16 and 17 show examples of common audio formats. By default, SDOUTS1 and SDOUTS2 are set high impedance when the IC is not outputting data to facilitate sharing the bus. Configure the interface in TDM mode using only slot 1 to transmit and receive mono PCM voice data. The IC's digital audio interfaces support both ADC to DAC loop-through and digital loopback. Loop-through allows the signal converted by the ADC to be routed to the DAC for playback. The signal is routed from the record path to the playback path in the digital audio interface to allow the IC's full complement of digital signal processing to be used. Loopback allows digital
74
Stereo Audio Codec with FLEXSOUND Technology
data input to either SDINS1 or SDINS2 to be routed from one interface to the other for output on SDOUTS2 or SDOUTS1. Both interfaces must be configured for the same sample rate, but the interface format need not be the same. This allows the IC to route audio data from one device to another, converting the data format as needed. Figure 15 shows the available digital signal routing options.
MAX98088
BCLKS1
LRCLKS1
SDOUTS1
SDINS1
DVDDS1 BCLKS2
LRCLKS2
SDOUTS2
SDINS2
DVDDS2
SEL1 BCLK1 LRCLK1 SDOUT1 SDIN1
SEL2 BCLK2 LRCLK2 SDOUT2 SDIN2 HIZOFF2 SDOEN2 DATA INPUT SDIEN2
DAI1 MAS1 BIT CLOCK FRAME CLOCK MAS1 HIZOFF1 SDOEN1 DATA INPUT SDIEN1
DAI2 MAS2 BIT CLOCK FRAME CLOCK MAS2
DATA OUTPUT
DATA OUTPUT
LBEN2 MUX LBEN1 LTEN1
+
DAI1 PLAYBACK PATH DAI2 PLAYBACK PATH
DAI1 RECORD PATH
Figure 15. Digital Audio Signal Routing
Table 9. Common Digital Audio Formats
MODE Left Justified I2S PCM TDM X = Don't care. 75 WCI1/WCI2 Set as desired 1 X X BCI1/BCI2 Set as desired 0 1 1 DLY1/DLY2 0 1 X X TDM1/TDM2 0 0 1 1 SLOTL1/SLOTL2 SLOTR1/SLOTR2 X X 0 Set as desired X X 0
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 10. Digital Audio Interface Registers
REGISTER BIT NAME DESCRIPTION DAI1/DAI2 Master Mode In master mode, DAI1/DAI2 outputs LRCLK and BCLK. In slave mode, DAI1/DAI2 accept LRCLK and BCLK as inputs. 0 = Slave mode 1 = Master mode DAI1/DAI2 Word Clock Invert TDM1/TDM2 = 0: 0 = Left-channel data is transmitted while LRCLK is low. 1 = Right-channel data is transmitted while LRCLK is low. TDM1/TDM2 = 1: Always set WCI = 0. DAI1/DAI2 Bit Clock Invert BCI1/BCI2 must be set to 1 when TDM1/TDM2 = 1. 0 = SDIN is accepted on the rising edge of BCLK. SDOUT is valid on the rising edge of BCLK. 1 = SDIN is accepted on the falling edge of BCLK. SDOUT is valid on the falling edge of BCLK. Master Mode: 0 = LRCLK transitions on the falling edge of BCLK. 1 = LRCLK transitions on the rising edge of BCLK. DAI1/DAI2 Data Delay DLY1/DLY2 has no effect when TDM1/TDM2 = 1. 0 = The most significant data bit is clocked on the first active BCLK edge after an LRCLK transition. 1 = The most significant data bit is clocked on the second active BCLK edge after an LRCLK transition. DAI1/DAI2 Time-Division Multiplex Mode (TDM Mode) Set TDM1/TDM2 when communicating with devices that use a frame synchronization pulse on LRCLK instead of a square wave. 0 = Disabled 1 = Enabled (BCI1/BCI2 must be set to 1) DAI1/DAI2 Wide Frame Sync Pulse Increases the width of the frame sync pulse to the full data width when TDM1/TDM2 = 1. FSW1/FSW2 has no effect when TDM1/TDM2 = 0. 0 = Disabled 1 = Enabled DAI1/DAI2 Audio Data Bit Depth Determines the maximum bit depth of audio being transmitted and received. Data is always 16 bit when TDM1/TMD2 = 0. 0 = 16 bits 1 = 24 bits
7
MAS1/MAS2
6
WCI1/WCI2
5
BCI1/BCI2
0x14/0x1C 4 DLY1/DLY2
2
TDM1/TDM2
1
FSW1/FSW2
0
WS1/WS2
76
Stereo Audio Codec with FLEXSOUND Technology
Table 10. Digital Audio Interface Registers (continued)
REGISTER BIT 7 OSR1 6 NAME DESCRIPTION ADC Oversampling Ratio Use the higher setting for maximum performance. Use the lower setting for reduced power consumption at the expense of performance. 00 = 96x 01 = 64x 10 = Reserved 11 = Reserved DAC Oversample Clock (DAC_OSR1/DAC_OSR2 1 = DAC input clock = PCLK/4 0 = DAC input clock = PCLK/2 DAI1/DAI2 BCLK Output Frequency When operating in master mode, BSEL1/BSEL2 set the frequency of BCLK. When operating in slave mode, BSEL1/BSEL2 have no effect. Select the lowest BCLK frequency that clocks all data input to the DAC and output by the ADC. 000 = BCLK disabled 001 = 64 x LRCLK 010 = 48 x LRCLK 011 = 128 x LRCLK (invalid for DHF1/DHF2 = 1) 100 = PCLK/2 101 = PCLK/4 110 = PCLK/8 111 = PCLK/16 DAI1/DAI2 Audio Port Selector Selects which port is used by DAI1/DAI2. 00 = None 01 = Port S1 10 = Port S2 11 = Reserved DAI1 Digital Loopthrough Connects the output of the record signal path to the input of the playback path. Data input to DAI1 from an external device is mixed with the recorded audio signal. 0 = Disabled 1 = Enabled DAI1/DAI2 Digital Audio Interface Loopback LBEN1 routes the digital audio input to DAI1 back out on DAI2. LBEN2 routes the digital audio input to DAI2 back out on DAI2. Selecting LBEN2 disables the ADC output data. 0 = Disabled 1 = Enabled DAI1/DAI2 DAC Mono Mix Mixes the left and right digital input to mono and routes the combined signal to the left and right playback paths. The left and right input data is attenuated by 6dB prior to the mono mix. 0 = Disabled 1 = Enabled
MAX98088
5 0x15/0x1D 2
DAC_OSR1/ DAC_OSR2
1
BSEL1/ BSEL2
0
7 SEL1/SEL2 6
5
LTEN1
0x16/0x1E 4 LBEN1/ LBEN2
3
DMONO1/ DMONO2
77
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 10. Digital Audio Interface Registers (continued)
REGISTER BIT NAME HIZOFF1/ HIZOFF2 DESCRIPTION Disable DA1/DAI2 Output High-Impedance Mode Normally SDOUT is set high impedance between data words. Set HIZOFF1/HIZOFF2 to force a level on SDOUT at all times. 0 = Disabled 1 = Enabled DAI1/DAI2 Record Path Output Enable DAI2 outputs data only if LBEN1 = 1. 0 = Disabled 1 = Enabled DAI1/DAI2 Playback Path Input Enable 0 = Disabled 1 = Enabled TDM Left Time Slot Selects which of the four slots is used for left data on DAI1/DAI2. If the same slot is selected for left and right audio, left audio is placed in the slot. 00 = Slot 1 01 = Slot 2 10 = Slot 3 11 = Slot 4 TDM Right Time Slot Selects which of the four slots is used for right data on DAI1/DAI2. If the same slot is selected for left and right audio, left audio is placed in the slot. 00 = Slot 1 01 = Slot 2 10 = Slot 3 11 = Slot 4 TDM Slot Delay Adds 1 BCLK cycle delay to the data in the specified TDM slot. 1xxx = Slot 4 delayed x1xx = Slot 3 delayed xx1x = Slot 2 delayed xxx1 = Slot 1 delayed
2
0x16/0x1E 1
SDOEN1/ SDOEN2
0
SDIEN1/ SDIEN2
7 SLOTL1/ SLOTL2 6
5 0x17/0x1F 4 3 2 1 0 SLOTDLY1/ SLOTDLY2 SLOTR1/ SLOTR2
78
Stereo Audio Codec with FLEXSOUND Technology MAX98088
WCI_ = 0, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT BCLK SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RIGHT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
WCI_ = 1, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT BCLK SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RIGHT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT BCLK SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RIGHT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
WCI_ = 0, BCI_ = 0, DLY_ = 1, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT BCLK SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RIGHT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 16. Non-TDM Data Format Examples
79
Stereo Audio Codec with FLEXSOUND Technology MAX98088
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1 LRCLK SDOUT BCLK SDIN
HI-Z L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 HI-Z
L15 L14 L13 L12 L11 L10 L9
L8 L7
L6 L5
L4 L3
L2
L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 1, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1 LRCLK SDOUT BCLK SDIN
HI-Z L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 HI-Z
L15 L14 L13 L12 L11 L10 L9
L8 L7
L6 L5
L4 L3
L2
L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 1 LRCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
SDOUT BCLK SDIN
L15 L14 L13 L12 L11 L10 L9
L8 L7
L6 L5
L4 L3
L2
L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 2, SLOTR_ = 3 LRCLK SDOUT
HI-Z L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 HI-Z
32 CYCLES
BCLK SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1 LRCLK 16 CYCLES SDOUT BCLK SDIN
HI-Z L L L L L L L L 1 1 1 1 R R R R HI-Z L L L L L L L L R R R
16 CYCLES
R R R R R
16 CYCLES
HI-Z
16 CYCLES
Figure 17. TDM Mode Data Format Examples 80
Stereo Audio Codec with FLEXSOUND Technology
The digital signal paths in the IC require a master clock (MCLK) between 10MHz and 60MHz to function. Internally, the MAX98088/MAX98089 requires a clock between 10MHz and 20MHz. A prescaler divides MCLK by 1, 2, or 4 to create the internal clock (PCLK). PCLK is used to clock all portions of the IC. The MAX98088/MAX98089 includes two digital audio signal paths, both capable of supporting any sample rate from 8kHz to 96kHz. Each path is independently configured to allow different sample rates. To accommodate a wide range of system architectures, three main clocking modes are supported: U PLL Mode: When operating in slave mode, enable the PLL to lock onto any LRCLK input. This mode requires the least configuration, but provides the lowest performance. Use this mode to simplify initial setup or when normal mode and exact integer mode cannot be used.
Clock Control
U Normal Mode: This mode uses a 15-bit clock divider to set the sample rate relative to PCLK. This allows high flexibility in both the PCLK and LRCLK frequencies and can be used in either master or slave mode. U Exact Integer Mode (DAI1 only): In both master and slave modes, common MCLK frequencies (12MHz, 13MHz, 16MHz, and 19.2MHz) can be programmed to operate in exact integer mode for both 8kHz and 16kHz sample rates. In these modes, the MCLK and LRCLK rates are selected by using the FREQ1 bits instead of the NI, and PLL control bits. U DAC Low-Power Mode: This mode bypasses the PLL for reduce power consumptions and uses fixed counters to generate the clocks. The DAI__DAC_LP bits override the overclock settings.
MAX98088
Table 11. Clock Control Registers
REGISTER BIT 5 0x10 4 PSCLK NAME DESCRIPTION MCLK Prescaler Generates PCLK, which is used by all internal circuitry. 00 = PCLK disabled 01 = 10MHz P MCLK P 20MHz (PCLK = MCLK) 10 = 20MHz P MCLK P 40MHz (PCLK = MCLK/2) 11 = 40MHz P MCLK P 60MHz (PCLK = MCLK/4) DAI1/DAI2 Sample Rate Used by the ALC to correctly set the dual-band crossover frequency and the excursion limiter to set the predefined corner frequencies. VALUE 0x0 0x11/0x19 5 SR1/SR2 0x1 0x2 0x3 0x4 0x5 4 0x6 0x7 SAMPLE RATE (kHz) Reserved 8 11.025 16 22.05 24 32 44.1 VALUE 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF SAMPLE RATE (kHz) 48 88.2 96 Reserved Reserved Reserved Reserved Reserved
7
6
81
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 11. Clock Control Registers (continued)
REGISTER BIT NAME DESCRIPTION Exact Integer Mode Overrides PLL1 and NI1 and configures a specific PCLK to LRCLK ratio. 3 VALUE 0x0 0x1 0x2 0x11 2 FREQ1 0x3 0x4 0x5 1 0x6 0x7 SAMPLE RATE Disabled Reserved Reserved Reserved Reserved Reserved Reserved Reserved VALUE 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF SAMPLE RATE PCLK = 12MHz, LRCLK = 8kHz PCLK = 12MHz, LRCLK = 16kHz PCLK = 13MHz, LRCLK = 8kHz PCLK = 13MHz, LRCLK = 16kHz PCLK = 16MHz, LRCLK = 8kHz PCLK = 16MHz, LRCLK = 16kHz PCLK = 19.2MHz, LRCLK = 8kHz PCLK = 19.2MHz, LRCLK = 16kHz
7
PLL1/PLL2
PLL Mode Enable (Slave Mode Only) PLL1/PLL2 enables a digital PLL that locks on to the externally supplied LRCLK frequency and automatically sets the LRCLK divider (NI1/NI2). 0 = Disabled 1 = Enabled Normal Mode LRCLK Divider When PLL1/PLL2 = 0, the frequency of LRCLK is determined by NI1/NI2. See Table 12 for common NI values. SAMPLE RATE 8kHz P LRCLK P 48kHz DHF1/DHF2 0 NI1/NI2 FORMULA
0x12/0x1A
6 5 4 3 2 1 0 7 6 5 4 3 2 1 NI1/ NI2
NI =
65536 x 96 x fLRCLK fPCLK 65536 x 48 x fLRCLK fPCLK
48kHz < LRCLK P 96kHz
1
NI =
0x13/0x1B
fLRCLK = LRCLK frequency fPCLK = Prescaled MCLK frequency (PCLK) Rapid Lock Mode Program NI1/NI2 to the nearest valid ratio and set NI1[0]/NI2[0] when PLL1/PLL2 = 1 to enable rapid lock mode. Normally, the PLL automatically calculates and dynamically adjusts NI1/NI2. When rapid lock mode is properly configured, the PLL starting point is much closer to the correct value, thus speeding up lock time. Wait one LRCLK period after programming NI1/NI2 before setting PLL1/PLL2 = 1.
0
NI1[0]/NI2[0]
82
Stereo Audio Codec with FLEXSOUND Technology
Table 11. Clock Control Registers (continued)
REGISTER BIT 7 NAME DESCRIPTION DAI_ DAC Low Power Select. These bits setup the clocks to be generated from fixed counters that bypass the PLL for DAC low power mode. VALUE 6 DAI2_DAC_LP 0x0 0x1 0x2 0x3 3 0x4 2 1 0 DAI1_DAC_LP 0x5 0x6 0x7 SETTING PLL derived clock PCLK = 128 x LRCLK PCLK = 192 x LRCLK PCLK = 256 x LRCLK PCLK = 384 x LRCLK PCLK = 768 x LRCLK PCLK = 1152 x LRCLK PCLK = 1536 x LRCLK VALUE 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF SETTING PCLK = 2304 x LRCLK Reserved Reserved Reserved Reserved Reserved Reserved Reserved
MAX98088
5 4 0x4F
3
DAC2DITHEN
DIA2 DAC Input Dither Enable DAC2DITHEN is recommended to be set when DAI2_DAC_LP = 0000. 0 = Disabled 1 = Enabled DIA1 DAC Input Dither 1 Enable DAC1DITHEN is recommended to be set when DAI1_DAC_LP = 0000. 0 = Disabled 1 = Enabled DIA2 Clock Gen Module Enable CGM1_EN has to be set along with CGM2_EN to enable the clock generation for the DAI2 DAC playback path. 0 = Disabled 1 = Enabled DIA1/Master Clock Gen Module Enable CGM1_EN enables the master clock generation, and need to be set for DAC playback or ADC record. 0 = Disabled 1 = Enabled
2
DAC1DITHEN
0x50 1 CGM2_EN
0
CGM1_EN
83
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 12. Common NI1/NI2 Values
LRCLK (kHz) PCLK (MHz) 8 10 11 11.2896 12 12.288 13 16 16.9344 18.432 20 13A9 11E0 116A 1062 1000 0F20 0C4A 0B9C 0AAB 09D5 11.025 1B18 18A2 1800 1694 160D 14D8 10EF 1000 0EB3 0D8C 12 1D7E 1ACF 1A1F 1893 1800 16AF 126F 116A 1000 0EBF 16 2752 23BF 22D4 20C5 2000 1E3F 1893 1738 1555 13A9 DHF1/2 = 0 22.05 3631 3144 3000 2D29 2C1A 29AF 21DE 2000 1D66 1B18 24 3AFB 359F 343F 3127 3000 2D5F 24DD 22D4 2000 1D7E 32 4EA5 477E 45A9 4189 4000 3C7F 3127 2E71 2AAB 2752 44.1 6C61 6287 6000 5A51 5833 535F 43BD 4000 3ACD 3631 48 75F7 6B3E 687D 624E 6000 5ABE 49BA 45A9 4000 3AFB 64 4EA5 477E 45A9 4189 4000 3C7F 3127 2E71 2AAB 2752 DHF1/2 = 1 88.2 6C61 6287 6000 5A51 5833 535F 43BD 4000 3ACD 3631 96 75F7 6B3E 687D 624E 6000 5ABE 49BA 45A9 4000 3AFB
Note: Values in bold are exact integers that provide maximum full-scale performance.
The sample rate conversion scheme enables the mixing of asynchronous audio data from the digital audio inter-
Sample Rate Converter
faces (SDIN1/SDIN2), and for the resulting mixed audio to output on either audio interface through SDOUT1 or SDOUT2.
DVST: 0dB TO -60dB SIDETONE DSTS MIX
DV1G: 0/6/12/18dB
+
MULTI BAND ALC DVEQ1: 0dB TO -15dB DVEQ2: 0dB TO -15dB
AUTOMATIC GAIN CONTROL MODE1 AVFLT ADLEN ADCL AVLG: 0/6/ 12/18dB AVL:0dB TO -15dB SRMIX_ MODE
NOISE GATE AUDIO/ VOICE FILTERS
5-BAND PARAMETRIC EQ EQ1EN
5-BAND PARAMETRIC EQ EQ2EN MIX AUDIO/ FILTERS DCB2 MIXDAL DACL DALEN
EXCURSION LIMITER AVRG: 0/6/ 12/18dB AVR:0dB TO -15dB
DV2: 0dB TO -15dB
SAMPLE RATE CONVERTER AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR DAREN
ADCR ADREN
DV1: 0dB TO -15dB
Figure 18. Sample Rate Converter 84
Stereo Audio Codec with FLEXSOUND Technology
Table 13. Sample Rate Converter
REGISTER BIT 4 3 2 1 0 NAME SRMIX_MODE SRMIX_ENL SRMIX_ENR SRC_ENL SRC_ENR Sample Rate Mix Mode 0 = (DAI1 + DAI2) 1 = (DAI1 + DAI2)/2 Sample Rate Mix Enable 0 = SRC mix disable 1 = SRC mix enable Sample Rate Converter Enable 0 = Sample rate converter disable 1 = Sample rate converter enable DESCRIPTION
MAX98088
0x21
Each digital signal path in the IC includes options for defining the path bandwidth (Figure 19). The playback and record paths connected to DAI1 support both voice and music filtering while the playback path connected to DAI2 supports music filtering only. The voice IIR filters provide greater than 70dB stopband attenuation at frequencies above fS/2 to reduce aliasing. Three selectable highpass filters eliminate unwanted low-frequency signals.
Passband Filtering
Use music mode when processing high-fidelity audio content. The music FIR filters reduce power consumption and are linear phase to maintain stereo imaging. An optional DC-blocking filter is available to eliminate unwanted DC offset. In music mode, a second set of FIR filters are available to support sample rates greater than 50kHz. The filters can be independently selected for DAI1 and DAI2 and support both the playback and record audio paths.
DVST: 0dB TO -60dB SIDETONE DSTS MIX
DV1G: 0/6/12/18dB
+
MULTI BAND ALC DVEQ1: 0dB TO -15dB DVEQ2: 0dB TO -15dB
AUTOMATIC GAIN CONTROL MODE1 AVFLT ADLEN ADCL AVLG: 0/6/ 12/18dB AVL:0dB TO -15dB SRMIX_ MODE
NOISE GATE AUDIO/ VOICE FILTERS
5-BAND PARAMETRIC EQ EQ1EN
5-BAND PARAMETRIC EQ EQ2EN MIX AUDIO/ FILTERS DCB2 MIXDAL DACL DALEN
EXCURSION LIMITER AVRG: 0/6/ 12/18dB AVR:0dB TO -15dB
DV2: 0dB TO -15dB
SAMPLE RATE CONVERTER
ADCR ADREN
DV1: 0dB TO -15dB
AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR DAREN
Figure 19. Digital Passband Filtering Block Diagram 85
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 14. Passband Filtering Registers
REGISTER BIT 7 6 5 AVFLT1 4 NAME MODE1 DESCRIPTION DAI1 Passband Filtering Mode 0 = Voice filters 1 = Music filters (recommended for fS > 24kHz) DAI1 ADC Highpass Filter Mode MODE1 0 1 AVFLT1 See Table 15 Select a nonzero value to enable the DC-blocking filter.
0x18 3 DHF1
DAI1 High Sample Rate Mode Selects the sample rate range. 0 = 8kHz P LRCLK P 48kHz 1 = 48kHz P LRCLK P 96kHz DAI1 DAC Highpass Filter Mode MODE1 DVFLT1 See Table 15 Select a nonzero value to enable the DC-blocking filter. 0 1
2 1 DVFLT1 0
3 0x20 0
DHF2
DAI2 High Sample Rate Mode Selects the sample rate range. 0 = 8kHz P LRCLK P 48kHz 1 = 48kHz < LRCLK P 96kHz DAI2 DC Blocking Filter Enables a DC-blocking filter on the DAI2 playback audio path. 0 = Disabled 1 = Enabled
DCB2
86
Stereo Audio Codec with FLEXSOUND Technology
Table 15. Voice Highpass Filters
AVFTL/DVFLT VALUE 000 INTENDED SAMPLE RATE N/A
0 -10 AMPLITUDE (dB) -20 -30 -40 -50 -60 0 200 400 600 800 1000 FREQUENCY (Hz)
MAX98088
FILTER RESPONSE Disabled
001/011
16kHz/8kHz
0 -10
AMPLITUDE (dB)
-20 -30 -40 -50 -60 0 200 400 600 800 1000 FREQUENCY (Hz) 0 -10
010/100
16kHz/8kHz
AMPLITUDE (dB)
-20 -30 -40 -50 LRCLK = 48kHz -60 0 200 400 600 800 1000 FREQUENCY (Hz)
101
8kHz to 48kHz
110/111
N/A
Reserved
87
Stereo Audio Codec with FLEXSOUND Technology MAX98088
The IC playback signal path includes automatic level control (ALC) and a 5-band parametric equalizer (EQ) (Figure 20). The DAI1 and DAI2 playback paths include separate ALCs controlled by a single set of registers. Two completely separate parametric EQs are included for the DAI1 and DAI2 playback paths.
Playback Path Signal Processing
The ALC can optionally be configured in dual-band mode. In this mode, the input signal is filtered into two bands with a 5kHz center frequency. Each band is routed through independent ALCs and then summed together. In multiband mode, both bands use the same parameters.
OUTPUT SIGNAL (dBFS) 0
Automatic Level Control The automatic level control (ALC) circuit ensures maximum signal amplitude without producing audible clipping. This is accomplished by a variable gain stage that works on a sample by sample basis to increase the gain up to 12dB. A look-ahead circuit determines if the next sample exceeds full scale and reduces the gain so that the sample is exactly full scale. A programmable low signal threshold determines the minimum signal amplitude that is amplified. Select a threshold that prevents the amplification of background noise. When the signal level drops below the low signal threshold, the ALC reduces the gain to 0dB until the signal increases above the threshold. Figure 21 shows an example of ALC input vs. output curves.
LOW-LEVEL -12 0 THRESHOLD ALC WITH ALCTH 000 OUTPUT SIGNAL (dBFS) 0
INPUT SIGNAL (dBFS)
DV1G: 0/6/12/18dB
+
MULTI BAND ALC DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ EQ1EN EXCURSION LIMITER AUDIO/ FILTERS DCB2 DVEQ2: 0dB TO -15dB
LOW-LEVEL THRESHOLD OUTPUT SIGNAL (dBFS)
MIX MIXDAL DACL DALEN
-12
0
INPUT SIGNAL (dBFS)
5-BAND PARAMETRIC EQ EQ2EN
ALC WITH ALCTH = 000
0
DV2: 0dB TO -15dB
DV1: 0dB TO -15dB
AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR DAREN
LOW-LEVEL THRESHOLD
-12
0
INPUT SIGNAL (dBFS)
ALC DISABLED
Figure 20. Playback Path Signal Processing Block Diagram 88
Figure 21. ALC Input vs. Output Examples
Stereo Audio Codec with FLEXSOUND Technology
Table 16. Automatic Level Control Registers
REGISTER BIT 7 NAME ALCEN DESCRIPTION ALC Enable Enables ALC on both the DAI1 and DAI2 playback paths. 0 = Disabled 1 = Enabled ALC and Excursion Limiter Release Time Sets the release time for both the ALC and Excursion Limiter. See the Excursion Limiter section for Excursion Limiter release times. ALC release time is defined as the time required to adjust the gain from 12dB to 0dB. VALUE 000 001 010 011 100 101 110 111 ALC RELEASE TIME (s) 8 4 2 1 0.5 0.25 Reserved Reserved
MAX98088
6
5
ALCRLS
0x43
4
3
ALCMB
Multiband Enable Enables dual-band processing with a 5kHz center frequency. SR1 and SR2 must be configured properly to achieve the correct center frequency for each playback path. 0 = Single-band ALC 1 = Dual-band ALC Low Signal Threshold Selects the minimum signal level to be boosted by the ALC. 000 = -JdB (low-signal threshold disabled) 001 = -12dB 010 = -18dB 011 = -24dB 100 = -30dB 101 = -36dB 110 = -42dB 111 = -48dB
1000 MAXIMUM RECOMMENDED FILTER Q fs = 8kHz 100 fs = 48kHz 10 fs = 96kHz 1
2
1
ALCTH
0
Parametric Equalizer The parametric EQ contains five independent biquad filters with programmable gain, center frequency, and bandwidth. Each biquad filter has a gain range of Q12dB and a center frequency range from 20Hz to 20kHz. Use a filter Q less than that shown in Figure 22 to achieve ideal frequency responses. Setting a higher Q results in nonideal frequency response. The biquad filters are series connected, allowing a total gain of Q60dB.
0.1 100 1000 10,000 100,000 CENTER FREQUENCY (Hz)
Figure 22. Maximum Recommended Filter Q vs. Frequency 89
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Use the attenuator at the EQ's input to avoid clipping the signal. The attenuator can be programmed for fixed attenuation or dynamic attenuation based on signal level. If the dynamic EQ clip detection is enabled, the signal level from the EQ is fed back to the attenuator circuit to determine the amount of gain reduction necessary to avoid clipping. The MAX98088/MAX98089 EV kit software includes a graphic interface for generating the EQ coefficients. The coefficients are sample rate dependent and stored in registers 0x52 through 0xB5.
Table 17. EQ Registers
REGISTER BIT 4 NAME EQCLP1/ EQCLP2 DESCRIPTION DAI1/DAI2 EQ Clip Detection Automatically controls the EQ attenuator to prevent clipping in the EQ. 0 = Enabled 1 = Disabled DAI1/DAI2 EQ Attenuator Provides attenuation to prevent clipping in the EQ when full-scale signals are boosted. DVEQ1/DVEQ2 operates only when EQ1EN/EQ2EN = 1 and EQCLP1/EQCLP2 = 1. VALUE 2 DVEQ1/DVEQ2 1 0x0 0x1 0x2 0x3 0x4 0x5 0 7 6 5 0x49 1 VS2EN VSEN ZDEN EQ2EN DAI2 EQ Enable 0 = Disabled 1 = Enabled DAI1 EQ Enable 0 = Disabled 1 = Enabled See the Click-and-Pop Reduction section. 0x6 0x7 GAIN (dB) 0 -1 -2 -3 -4 -5 -6 -7 VALUE 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF GAIN (dB) -8 -9 -10 -11 -12 -13 -14 -15
3
0x30/0x32
0
EQ1EN
90
Stereo Audio Codec with FLEXSOUND Technology
The IC includes separate digital level control for the DAI1 and DAI2 playback audio paths. The DAI1 signal path
Playback Level Control
allows boost when MODE1 = 0 and attenuation in any mode. The DAI2 signal path allows attenuation only.
MAX98088
DV1G: 0/6/12/18dB
+
MULTI BAND ALC DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ EQ1EN EXCURSION LIMITER AUDIO/ FILTERS DCB2 DVEQ2: 0dB TO -15dB
5-BAND PARAMETRIC EQ EQ2EN MIX MIXDAL DACL DALEN
DV2: 0dB TO -15dB
DV1: 0dB TO -15dB
AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR DAREN
Figure 23. Playback Level Control Block Diagram
Table 18. DAC Playback Level Control Register
REGISTER BIT 7 NAME DV1M/DV2M DAI1/DAI2 Mute 0 = Disabled 1 = Enabled DAI1 Voice Mode Gain DV1G only applies when MODE1 = 0. 00 = 0dB 01 = 6dB 10 = 12dB 11 = 18dB DAI1/DAI2 Attenuation VALUE 0x0 2 DV1/DV2 1 0x1 0x2 0x3 0x4 0x5 0 0x6 0x7 GAIN (dB) 0 -1 -2 -3 -4 -5 -6 -7 VALUE 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF GAIN (dB) -8 -9 -10 -11 -12 -13 -14 -15 91 DESCRIPTION
5 DV1G 4
0x2F/0x31
3
Stereo Audio Codec with FLEXSOUND Technology MAX98088
The IC's stereo DAC accepts input from two digital audio paths. The DAC mixer routes any audio path to the left and right DACs (Figure 24).
DAC Input Mixers
DV1G: 0/6/12/18dB
+
MULTI BAND ALC DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ EQ1EN EXCURSION LIMITER AUDIO/ FILTERS DCB2 DVEQ2: 0dB TO -15dB
5-BAND PARAMETRIC EQ EQ2EN MIX MIXDAL DACL DALEN
DV2: 0dB TO -15dB
DV1: 0dB TO -15dB
AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR DAREN
Figure 24. DAC Input Mixer Block Diagram
Table 19. DAC Input Mixer Register
REGISTER BIT 7 6 5 0x22 4 3 2 1 0 MIXDAR MIXDAL NAME Left DAC Input Mixer 1xxx = DAI1 left channel x1xx = DAI1 right channel xx1x = DAI2 left channel xxx1 = DAI2 right channel Right DAC Input Mixer 1xxx = DAI1 left channel x1xx = DAI1 right channel xx1x = DAI2 left channel xxx1 = DAI2 right channel DESCRIPTION
92
Stereo Audio Codec with FLEXSOUND Technology
The IC includes a single differential receiver amplifier. The receiver amplifier is designed to drive a 32I earpiece speaker. In cases where a single transducer is used for the loudspeaker and receiver, use the SPKBYP switch to route the receiver amplifier output to the left speaker outputs. The receiver amplifier can also be configured as stereo singleended line outputs using the I2C interface.
Receiver Amplifier
MAX98088
RECVOLL: +8dB TO -62dB MIX 0dB RECLEN MIXRECL RECVOLR: +8dB TO -62dB MIX LINEMODE MIXRECR 0dB RECREN SPKBYP RECBYP
RECP/ LOUTL/ RXINP
RECN/ LOUTR/ RXINN
SPKLP +6dB SPLEN DACL DALEN SPKLN
DACR DAREN
Figure 25. Receiver Amplifier Block Diagram
93
Stereo Audio Codecs with FLEXSOUND Technology MAX98088/MAX98089
Receiver Output Mixer The IC's receiver amplifier accepts input from the stereo DAC, the line inputs (single-ended or differential), and the MIC inputs. Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the mixed signal can be configured to attenuate 6dB, 9dB, or 12dB.
Table 20. Receiver Output Mixer Register
REGISTER BIT 7 6 5 0x28 4 3 2 1 0 7 6 5 0x29 4 3 2 1 0 7 LINE_MODE MIXRECR MIXRECL NAME DESCRIPTION Left Receiver Output Mixer 1xxxxxxx = Right DAC x1xxxxxx = MIC1 xx1xxxxx = MIC2 xxx1xxxx = INA2 (INADIFF = 0) or INA2-INA1 (INADIFF = 1) xxxx1xxx = INA1 xxxxx1xx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1) xxxxxx1x = INB1 xxxxxxx1 = Left DAC Right Receiver Output Mixer 1xxxxxxx = Left DAC x1xxxxxx = MIC1 xx1xxxxx = MIC2 xxx1xxxx = INA2 (INADIFF = 0) or INA2-INA1 (INADIFF = 1) xxxx1xxx = INA1 xxxxx1xx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1) xxxxxx1x = INB1 xxxxxxx1 = Right DAC Receiver Output Mode. Configures receive path output mode between BTL and stereo line output. 0 = BTL 1 = Stereo line output Right Receiver Mixer Gain Select 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB Left Receiver Mixer Gain Select 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB
3 0x2A 2 1 0 0
MIXRECR _GAIN
MIXRECL _GAIN
94
Stereo Audio Codecs with FLEXSOUND Technology
Receiver Output Volume
MAX98088/MAX98089
Table 21. Receiver Output Level Register
REGISTER BIT 7 4 NAME RECLM/ RECRM Receiver Output Mute 0 = Disabled 1 = Enabled Receiver Output Volume Level VALUE 0x00 3 0x01 0x02 0x03 0x04 0x3B/0x3C 2 0x05 RECVOLL/ RECVOLR 0x06 0x07 0x08 1 0x09 0x0A 0x0B 0x0C 0 0x0D 0x0E 0x0F VOLUME (dB) -62 -58 -54 -50 -46 -42 -38 -35 -32 -29 -26 -23 -20 -17 -14 -12 VALUE 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F VOLUME (dB) -10 -8 -6 -4 -2 0 +1 +2 +3 +4 +5 +6 +6.5 +7 +7.5 +8 DESCRIPTION
95
Stereo Audio Codec with FLEXSOUND Technology MAX98088
The IC integrates a stereo filterless Class D amplifier that offers much higher efficiency than Class AB without the typical disadvantages. The high efficiency of a Class D amplifier is due to the switching operation of the output stage transistors. In a Class D amplifier, the output transistors act as current steering switches and consume negligible additional power. Any power loss associated with the Class D output stage is mostly due to the I2R loss of the MOSFET on-resistance, and quiescent current overhead.
Speaker Amplifiers
The theoretical best efficiency of a linear amplifier is 78%, however, that efficiency is only exhibited at peak output power. Under normal operating levels (typical music reproduction levels), efficiency falls below 30%, whereas the IC's Class D amplifier still exhibits 80% efficiency under the same conditions. Traditional Class D amplifiers require the use of external LC filters or shielding to meet EN55022B and FCC electromagnetic-interference (EMI) regulation standards. Maxim's patented active emissions limiting edge-rate control circuitry reduces EMI emissions.
SPVOLL: +8dB TO -62dB MIX DACL DALEN MIXSPL +6dB SPLEN POWER/ DISTORTION LIMITER
SPKLVDD SPKLP SPKLN SPKLGND SPKRVDD SPKRP
DACR DAREN
MIX SPVOLR: +8dB TO -62dB
+6dB SPREN
SPKRN SPKRGND
MIXSPR
Figure 26. Speaker Amplifier Path Block Diagram
96
Stereo Audio Codec with FLEXSOUND Technology
Speaker Output Mixers The IC's speaker amplifiers accept input from the stereo DAC, the line inputs (single-ended ore differential), and the MIC inputs. Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the mixer can be configured to attenuate the signal by 6dB, 9dB or 12dB.
MAX98088
Table 22. Speaker Output Mixer Register
REGISTER BIT 7 6 5 0x2B 4 3 2 1 0 7 6 5 0x2C 4 3 2 1 0 3 2 0x2D 1 0 MIXSPL _GAIN MIXSPR _GAIN MIXSPR MIXSPL NAME DESCRIPTION Left Speaker Output Mixer 1xxxxxxx = Right DAC x1xxxxxx = MIC1 xx1xxxxx = MIC2 xxx1xxxx = INA2 (INADIFF = 0) or INA2-INA1 (INADIFF = 1) xxxx1xxx = INA1 xxxxx1xx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1) xxxxxx1x = INB1 xxxxxxx1 = Left DAC Right Speaker Output Mixer 1xxxxxxx = Left DAC x1xxxxxx = MIC1 xx1xxxxx = MIC2 xxx1xxxx = INA2 (INADIFF = 0) or INA2-INA1 (INADIFF = 1) xxxx1xxx = INA1 xxxxx1xx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1) xxxxxx1x = INB1 xxxxxxx1 = Right DAC Right Speaker Mixer Gain Select 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB Left Speaker Mixer Gain Select 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB
97
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Speaker Output Volume
Table 23. Speaker Output Mixer Register
REGISTER BIT 7 NAME SPLM/SPRM DESCRIPTION Left/Right Speaker Output Mute 0 = Disabled 1 = Enabled Left/Right Speaker Output Volume Level 4 VALUE 0x00 0x01 0x02 0x03 0x3D/0x3E 3 SPVOLL/SPVOLR 0x04 0x05 0x06 0x07 0x08 2 0x09 0x0A 0x0B 0x0C 1 0x0D 0x0E 0x0F VOLUME (dB) -62 -58 -54 -50 -46 -42 -38 -35 -32 -29 -26 -23 -20 -17 -14 -12 VALUE 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F VOLUME (dB) -10 -8 -6 -4 -2 0 +1 +2 +3 +4 +5 +6 +6.5 +7 +7.5 +8
The IC includes signal processing to improve the sound quality of the speaker output and protect transducers from damage. An excursion limiter dynamically adjusts the highpass corner frequency, while a power limiter and distortion limiter prevent the amplifier from outputting too much distortion or power. The excursion limiter is located in the DSP while the distortion limiter and power limiter control the analog volume control (Figure 28). All three limiters analyze the speaker amplifier's output signal to determine when to take action. Excursion Limiter The excursion limiter is a dynamic highpass filter that monitors the speaker outputs and increases the highpass corner frequency when the speaker amplifier's output exceeds a predefined threshold. The filter smoothly
Speaker Amplifier Signal Processing
transitions between the high and low corner frequency to prevent unwanted artifacts. The filter can operate in four different modes: U Fixed-Frequency Preset Mode. The highpass corner frequency is fixed at the upper corner frequency and does not change with signal level. U Fixed-Frequency Programmable Mode. The highpass corner frequency is fixed to that specified by the programmable biquad filter. U Preset Dynamic Mode. The highpass filter automatically slides between a preset upper and lower corner frequency based on output signal level. U User-Programmable Dynamic Mode. The highpass filter slides between a user-programmed biquad filter on the low side to a predefined corner frequency on the high side.
98
Stereo Audio Codec with FLEXSOUND Technology
The transfer function for the user-programmable biquad is: b + b1z -1 + b 2z -2 H(z) = 0 1 + a 1z -1 + a 2z -2 The coefficients b0, b1, b2, a1, and a2 are sample rate dependent and stored in registers 0xB4 through 0xC7. Store b0, b1, and b2 as positive numbers. Store a1 and a2 as negated two's complement numbers. Separate filters can be stored for the DAI1 and DAI2 playback paths. The MAX98088/MAX98089 EV kit software includes a graphic interface for generating the user-programmable biquad coefficients. Note: Only change the excursion limiter settings when the signal path is disabled to prevent undesired artifacts.
MAX98088
DV1G: 0/6/12/18dB
+
MULTI BAND ALC DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ EQ1EN EXCURSION LIMITER AUDIO/ FILTERS DCB2 DVEQ2: 0dB TO -15dB MIX SPVOLL: +8dB TO -62dB +6dB SPLEN MIXSPL MIX MIXDAL DACL DALEN SPKRP MIX SPVOLR: MIXSPR +8dB TO -62dB AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR DAREN +6dB SPREN SPKRGND SPKRN SPKLGND POWER/ DISTORTION LIMITER SPKRVDD SPKLVDD SPKLP SPKLN
5-BAND PARAMETRIC EQ EQ2EN
DV2: 0dB TO -15dB
DV1: 0dB TO -15dB
Figure 27. Speaker Amplifier Signal Processing Block Diagram
99
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 24. Excursion Limiter Registers
REGISTER BIT 6 NAME DESCRIPTION Excursion Limiter Corner Frequency The excursion limiter has limited sliding range and minimum corner frequencies. Listed below are all the valid filter combinations. LOWER CORNER UPPER CORNER MINIMUM BIQUAD DHPUCF DHPLCF FREQUENCY FREQUENCY CORNER FREQUENCY Excursion limiter disabled -- 000 00 400Hz -- 001 00 600Hz -- 010 00 800Hz 1kHz Programmable using biquad 200Hz 400Hz 400Hz 600Hz -- -- 100Hz -- -- 011 100 000 001 010 00 00 11 01 10
5
DHPUCF
4
0x41 1
DHPLCF 0
6
0x43
5
ALCRLS
4
3
2 0x42 1 DHPTH
0
400Hz 800Hz -- 011 10 Programmable 400Hz 200Hz 001 11 using biquad Programmable 600Hz 300Hz 010 11 using biquad Programmable 800Hz 400Hz 011 11 using biquad Programmable 1kHz 500Hz 100 11 using biquad ALC and Excursion Limiter Release Time Sets the release time for both the ALC and Excursion Limiter. See the Automatic Level Control section for ALC release times. Excursion limiter release time is defined as the time required to slide from the high corner frequency to the low corner frequency. VALUE EXCURSION LIMITER RELEASE TIME (s) 000 4 001 2 010 1 011 0.5 100 0.25 101 0.25 110 Reserved 111 Reserved Excursion Limiter Threshold Measured at the Class D speaker amplifier outputs. Signals above the threshold use the upper corner frequency. Signals below the threshold use the lower corner frequency. VBAT must correctly reflect the voltage of SPKLVDD to achieve accurate thresholds. 000 = 0.34VP 001 = 0.71VP 010 = 1.30VP 011 = 1.77VP 100 = 2.33VP 101 = 3.25VP 110 = 4.25VP 111 = 4.95VP
100
Stereo Audio Codec with FLEXSOUND Technology
Power Limiter The IC's power limiter tracks the RMS power delivered to the loudspeaker and briefly mutes the speaker amplifier output if the speaker is at risk of sustaining permanent damage. Loudspeakers are typically damaged when the voice coil overheats due to extended operation above the rated power. During normal operation, heat generated in the voice coil is transferred to the speaker's magnet, which transfers heat to the surrounding air. For the voice coil to overheat, both the voice coil and the magnet must overheat. The result is that a loudspeaker can operate above its rated power for a significant time before it heats sufficiently to cause damage. The IC's power limiter includes user-programmable time constants and power thresholds to match a wide range of loudspeakers. Program the power limiter's threshold to match the loudspeaker's rated power handling. This can be determined through measurement or the loudspeaker's specification. Program time constant 1 to match the voice coil's thermal time constant. Program time constant 2 to match the magnet's thermal time constant. The time constants can be determined by plotting the voice coil's resistance vs. time as power is applied to the speaker.
MAX98088
Table 25. Power Limiter Registers
REGISTER BIT NAME DESCRIPTION Power Limiter Threshold If the RMS output power from the speaker amplifiers exceeds this threshold, the output is briefly muted to protect the speaker. The threshold is measured in watts assuming an 8I load. VBAT must correctly reflect the voltage of SPKLVDD/SPKRVDD to achieve accurate thresholds. VALUE 6 PWRTH 0x0 0x1 5 0x2 0x3 0x4 0x44 0x5 4 0x6 0x7 2 THRESHOLD (W) Power limiter disabled 0.05 0.06 0.09 0.11 0.13 0.18 0.22 VALUE 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF THRESHOLD (W) 0.27 0.35 0.48 0.72 1.00 1.43 1.57 1.80
7
Power Limiter Weighting Factor Determines the balance between time constant 1 and 2 to match the dominance of each time constant in the loudspeaker. VALUE 000 T1 (%) 50 62.5 75 87.5 100 12.5 25 37.5 T2 (%) 50 37.5 25 12.5 0 87.5 75 62.5
1
PWRK
001 010 011 100 101 110 111
0
101
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 25. Power Limiter Registers (continued)
REGISTER BIT 7 NAME DESCRIPTION Power Limiter Time Constant 2 Select a value that matches the thermal time constant of the loudspeaker's magnet. VALUE 6 PWRT2 5 0x0 0x1 0x2 0x3 0x4 0x5 4 0x45 3 0x6 0x7 TIME CONSTANT (min) Disabled 0.50 0.67 0.89 1.19 1.58 2.11 2.81 VALUE 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF TIME CONSTANT (min) 3.75 5.00 6.66 8.88 Reserved Reserved Reserved Reserved
Power Limiter Time Constant 1 Select a value that matches the thermal time constant of the loudspeaker's voice coil. VALUE TIME CONSTANT (s) Disabled 0.50 0.67 0.89 1.19 1.58 2.11 2.81 VALUE 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF TIME CONSTANT (s) 3.75 5.00 6.66 8.88 Reserved Reserved Reserved Reserved
2 PWRT1 1
0x0 0x1 0x2 0x3 0x4 0x5
0
0x6 0x7
Distortion Limiter The IC's distortion limiter ensures that the speaker amplifier's output does not exceed the programmed THD+N limit. The distortion limiter analyzes the Class D output duty cycle to determine the percentage of the waveform that is clipped. If the distortion exceeds the programmed threshold, the output gain is reduced.
102
Stereo Audio Codec with FLEXSOUND Technology
Table 26. Distortion Limiter Registers
REGISTER BIT 7 6 NAME Distortion Limit Measured in % THD+N. VALUE 0x0 0x1 5 0x46 4 THDCLP 0x2 0x3 0x4 0x5 0x6 0x7 THD+N LIMIT (%) Limiter disabled <1 1 2 4 6 8 10 VALUE 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF THD+N LIMIT (%) 12 14 16 18 20 21 22 24 DESCRIPTION
MAX98088
0
THDT1
Distortion Limiter Release Time Constant Duration of time required for the speaker amplifier's output gain to adjust back to the nominal level after a large signal has passed. 0 = 1.4s 1 = 2.8s
Headphone
DirectDrive Headphone Amplifier Traditional single-supply headphone amplifiers have outputs biased at a nominal DC voltage (typically half the supply). Large coupling capacitors are needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both headphone and headphone amplifier. Maxim's second-generation DirectDrive architecture uses a charge pump to create an internal negative supply voltage. This allows the headphone outputs of the ICs to be biased at GND while operating from a single supply (Figure 1). Without a DC component, there is no need for the large DC-blocking capacitors. Instead of two large (220F typ) capacitors, the IC's charge pump requires 3 small ceramic capacitors, conserving board space, reducing cost, and improving the frequency response of the headphone amplifier. Charge Pump The dual-mode charge pump generates both the positive and negative power supply for the headphone amplifier. To maximize efficiency, both the charge pump's
switching frequency and output voltage change based on signal level. When the input signal level is less than 10% of PVDD, the switching frequency is reduced to a low rate. This minimizes switching losses in the charge pump. When the input signal exceeds 10% of PVDD, the switching frequency increases to support the load current. For input signals below 25% of PVDD, the charge pump generates Q(PVDD/2) to minimize the voltage drop across the amplifier's power stage and thus improve efficiency. Input signals that exceed 25% of PVDD cause the charge pump to output QPVDD. The higher output voltage allows for full output power from the headphone amplifier. To prevent audible gliches when transitioning from the Q(PVDD/2) output mode to the QPVDD output mode, the charge pump transitions very quickly. This quick change draws significant current from PVDD for the duration of the transition. The bypass capacitor on PVDD supplies the required current and prevents droop on PVDD. The charge pump's dynamic switching mode can be turned off through the I2C interface. The charge pump can then be forced to output either Q(PVDD/2) or QPVDD regardless of input signal level.
103
Stereo Audio Codec with FLEXSOUND Technology MAX98088
VDD
VDD/2
Class H Operation A Class H amplifier uses a Class AB output stage with power supplies that are modulated by the output signal. In the case of the ICs, two nominal power-supply differentials of 1.8V (+0.9V to -0.9V) and 3.6V (+1.8V to -1.8V) are available from the charge pump. Figure 29 shows the operation of the output-voltage-dependent power supply
GND CONVENTIONAL AMPLIFIER BIASING SCHEME +VDD
1.8V 0.9V VTH_H HPVDD
TBD
GND
VTH_L -0.9V -1.8V
OUTPUT VOLTAGE
HPVSS
TBD
DirectDrive AMPLIFIER BIASING SCHEME
-VDD (VSS)
Figure 28. Traditional Amplifier Output vs. DirectDrive Output
Figure 29. Class H Operation
DACL DALEN DACR DAREN MIXHPL_ PATH SEL HPVOLL: +3dB TO -67dB HPLEN MIXHPR_ PATH SEL
MIX
HPL HPSNS
MIXHPL
MIX
HPVOLR: +3dB TO -67dB
HPR
MIXHPR
HPREN
Figure 30. Headphone Amplifier Block Diagram 104
Stereo Audio Codec with FLEXSOUND Technology
Headphone Output Mixers The headphone amplifier mixer accepts input from the stereo DAC, the line inputs (single-ended or differential), and the MIC inputs. Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the mixer can be configured to attenuate the signal by 6dB, 9dB, or 12dB. The stereo DAC can bypass the headphone mixers, and be connected directly to the headphone amplifiers to provide lower power consumption.
MAX98088
Table 27. Headphone Output Mixer Register
REGISTER BIT 7 6 5 0x25 4 3 2 1 0 7 6 5 0x26 4 3 2 1 0 5 MIXHPR_ PATH SEL MIXHPL_ PATH SEL MIXHPR MIXHPL NAME DESCRIPTION Left Headphone Output Mixer 1xxxxxxx = Right DAC x1xxxxxx = MIC1 xx1xxxxx = MIC2 xxx1xxxx = INA2 (INADIFF = 0) or INA2 - INA1 (INADIFF = 1) xxxx1xxx = INA1 xxxxx1xx = INB2 (INBDIFF = 0) or INB2 - INB1 (INBDIFF = 1) xxxxxx1x = INB1 xxxxxxx1 = Left DAC Right Headphone Output Mixer 1xxxxxxx = Left DAC x1xxxxxx = MIC1 xx1xxxxx = MIC2 xxx1xxxx = INA2 (INADIFF = 0) or INA2 - INA1 (INADIFF = 1) xxxx1xxx = INA1 xxxxx1xx = INB2 (INBDIFF = 0) or INB2 - INB1 (INBDIFF = 1) xxxxxx1x = INB1 xxxxxxx1 = Right DAC Right Headphone Mixer Path Select 0 = Directly connect to the right DAC (bypass right headphone output mixer) 1 = Right headphone output mixer Left Headphone Mixer Path Select 0 = Directly connect to the left DAC (bypass left headphone output mixer) 1 = Left headphone output mixer Right Headphone Mixer Gain Select 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB Left Headphone Mixer Gain Select 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB
4
0x27
3 2 1 0
MIXHPR _GAIN
MIXHPL _GAIN
105
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Headphone Output Volume
Table 28. Headphone Output Level Register
REGISTER BIT 7 NAME HPLM/HPRM Headphone Output Mute 0 = Disabled 1 = Enabled Left/Right Headphone Output Volume Level VALUE 4 0x00 0x01 0x02 0x03 0x39/0x3A 3 HPVOLL/HPVOLR 2 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 1 0x0B 0x0C 0x0D 0 0x0E 0x0F VOLUME (dB) -67 -63 -59 -55 -51 -47 -43 -40 -37 -34 -31 -28 -25 -22 -19 -17 VALUE 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F VOLUME (dB) -15 -13 -11 -9 -7 -5 -4 -3 -2 -1 0 +1 +1.5 +2 +2.5 +3 DESCRIPTION
106
Stereo Audio Codec with FLEXSOUND Technology
The IC's includes two output bypass switches that solve common applications problems. When a single transducer is used for the loudspeaker and receiver, the need exists for two amplifiers to power the same transducer. Bypass switches connect the IC's receiver amplifier output to the speaker amplifier's output, allowing either amplifier to power the same transducer. In systems where
Output Bypass Switches
an external receiver amplifier is used, route its output to the left speaker through RECP/RXINP and RECN/RXINN, bypassing the Class D amplifier. In systems where an external amplifier drives both the receiver and the IC's line input, one of the differential signals can be disconnected from the receiver when not needed by passing it through the analog switch that connects RECP/RXINP to RECN/RXINN.
MAX98088
0dB RECLEN 0dB RECREN RECBYP SPKBYP
RECP/RXINP
10I* 0dB EXTERNAL RECEIVER AMP RECLEN 0dB RECREN RECBYP SPKBYP
RECP/RXINP
0dB RECLEN
RECP/RXINP
EXTERNAL RECEIVER AMP
RECN/RXINN
10I*
RECN/RXINN
0dB RECREN RECBYP SPKBYP
RECN/RXINN
SPKLVDD SPKLP +6dB SPLEN POWER/DISTORTION LIMITER *OPTIONAL 10I RESISTORS IMPROVE DISTORTION THROUGH THE ANALOG SWITCH. SPEAKER AMPLIFIER BYPASS USING AN EXTERNAL RECEIVER AMPLIFIER SPKLN SPKLGND +6dB SPLEN POWER/DISTORTION LIMITER
SPKLVDD SPKLP SPKLN SPKLGND +6dB SPLEN POWER/DISTORTION LIMITER
SPKLVDD SPKLP SPKLN SPKLGND
SPEAKER AMPLIFIER BYPASS USING THE INTERNAL RECEIVER AMPLIFIER
CONTROLLING AN EXTERNAL RECEIVE AMPLIFIER AND SPEAKER
Figure 31. Output Bypass Switch Block Diagrams
Table 29. Output Bypass Switches Register
REGISTER BIT 7 4 NAME INABYP MIC2BYP See the Microphone Inputs section. RXINP to RXINN Bypass Switch Shorts RXINP to RXINN allowing a signal to pass through the ICs. Disable the receiver amplifier when RECBYP = 1. 0 = Disabled 1 = Enabled RXIN to SPKL Bypass Switch Shorts RXINP/RXINN to SPKLP/SPKLN allowing either the internal or an external receiver amplifier to power the left speaker. Disable the left speaker amplifier when SPKBYP = 1. 0 = Disabled 1 = Enabled DESCRIPTION
1 0x4A
RECBYP
0
SPKBYP
107
Stereo Audio Codec with FLEXSOUND Technology MAX98088
The IC includes extensive click-and-pop reduction circuitry. The circuitry minimizes clicks and pops at turn-on, turn-off, and during volume changes. Zero-crossing detection is implemented on all analog PGAs and volume controls to prevent large glitches when volume changes are made. Instead of making a volume change immediately, the change is made when the audio signal crosses the midpoint. If no zero-crossing occurs within the timeout window, the change is forced. Volume slewing breaks up large volume changes into the smallest available step size and the steps through each step between the initial and final volume setting. When
Click-and-Pop Reduction
enabled, volume slewing also occurs at device turn-on and turn-off. During turn-on the volume is set to mute before the output is enabled. Once the output is on, the volume ramps to the desired level. At turn-off the volume is ramped to mute before the outputs are disabled. When there is no audio signal zero-crossing detection can prevent volume slewing from occurring. Enable enhanced volume slewing to prevent the volume controller from requesting another volume level until the previous one has been set. Each step in the volume ramp then occurs after a zero crossing has occurred in the audio signal or the timeout window has expired. During turn-off, enhance volume slewing is always disabled.
Table 30. Click-and-Pop Reduction Register
REGISTER BIT NAME DESCRIPTION Enhanced Volume Smoothing During volume slewing, the controller waits for each step in the ramp to be applied before sending the next step. When zero-crossing detection is enabled this prevents large steps in the output volume when no zero crossings are detected. 0 = Enabled 1 = Disabled Applies to volume changes in HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR. Volume Adjustment Smoothing Volume changes are smoothed by stepping through intermediate steps. Also ramps the volume from minimum to the programmed value at turn-on and back to minimum at turn-off. 0 = Enabled 1 = Disabled Applies to volume changes in HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR. Zero-Crossing Detection Holds volume changes until there is a zero crossing in the audio signal. This reduces click and pop during volume changes (zipper noise). If no zero crossing is detected within 100ms, the volume change is forced. 0 = Enabled 1 = Disabled Applies to volume changes in PGAM1, PGAM2, PGAOUTA, PGAOUTB, PGAOUTC, HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR. See the 5-Band Parametric EQ section.
7
VS2EN
6 0x47
VSEN
5
ZDEN
1 0
EQ2EN EQ1EN
108
Stereo Audio Codec with FLEXSOUND Technology
The IC features jack detection that can detect the insertion and removal of a jack as well as the load type. When a jack is detected, an interrupt on IRQ can be triggered to alert the microcontroller of the event. Figure 32 shows the typical configuration for jack detection.
Jack Detection
Jack Detection and Removal When the IC is in normal operation and the MICBIAS is enabled, jack insertion and removal can be detected
through JACKSNS. To detect a jack insertion and removal, the ICs must be powered on and MICBIAS enabled. Set JDETEN, MBEN, BIASEN, and VCMEN bits to enable jack detection circuitry. JACKSNS is pulled up by MICBIAS as long as no load is applied to JACKSNS. Table 31 shows the change in JKSNS that occurs when a jack is inserted and removed.
MAX98088
HPL
MICBIAS JACKSNS
HPR
MIC1P
Figure 32. Typical Configuration for Jack Detection
Table 31. Change in JKSNS Upon Jack Insertion
JACK TYPE MBEN = 1, BIASEN = 1, VCMEN = 1
GND
GND
R
L
JKSNS: 1 e 0
MIC
GND
R
L
JKSNS: 1 e 0
Table 32. Change in JKSNS Upon Jack Removal
JACK TYPE MBEN = 1, BIASEN = 1, VCMEN = 1
GND
GND
R
L
JKSNS: 0 e 1
MIC
GND
R
L
JKSNS: 0 e 1
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Stereo Audio Codec with FLEXSOUND Technology MAX98088
Table 33. Jack Detection Registers
REGISTER 0x02 (Read Only) BIT NAME DESCRIPTION JACKSNS State Reports the status of JACKSNS when JDETEN = 1, MBEN = 1, BIASEN = 1, and VCMEN = 1. 0 = JACKSNS low 1 = JACKSNS high Jack Detection Enable 0 = Disabled 1 = Enabled Jack Detection Debounce Configures the debounce time for setting JDET. 00 = 25ms 01 = 50ms 10 = 100ms 11 = 200ms
6
JKSNS
7
JDETEN
0x4B
1 JDEB 0
The IC measures the voltage applied to SPKLVDD (typically the battery voltage) and reports the value in register 0x03. This value is also used by the speaker limiter circuitry to set accurate thresholds. When the battery measurement function is disabled, the battery voltage is user programmable.
Battery Measurement
Table 34. Battery Measurement Registers
REGISTER BIT 4 3 0x03 2 1 0 7 6 0x51 3 2 1 0 SHDN VBATEN PERFMODE HPPLYBCK PWRSV8K PWRSV VBAT NAME DESCRIPTION Battery Voltage Read VBAT when VBATEN = 1 to determine VSPKLVDD. Program VBAT when VBATEN = 0 to allow proper speaker amplifier signal processing. Calculate the battery voltage using the following formula: VBATTERY = 2.55V + [VBAT/10] See Power Management Battery Measurement Enable. Enables an internal ADC to measure VSPKLVDD. 0 = Disabled (register 0x03 readable and writeable) 1 = Enabled (register 0x03 read only) See the Power Management section. See the Power Management section. See the Power Management section. See the Power Management section.
110
Stereo Audio Codec with FLEXSOUND Technology
The IC uses register 0x00 and IRQ to report the status of various device functions. The status register bits are set when their respective events occur, and cleared upon reading the register. Device status can be determined
Device Status
either by poling register 0x00 or configuring the IRQ to pull low when specific events occur. IRQ is an opendrain output that requires a pullup resistor for proper operation. Register 0x0F determines which bits in the status register trigger IRQ to pull low.
MAX98088
Table 35. Status and Interrupt Registers
REGISTER BIT 7 NAME CLD DESCRIPTION Full Scale 0 = All digital signals are less than full scale. 1 = The DAC or ADC signal path has reached or exceeded full scale. This typically indicates clipping. Volume Slew Complete SLD reports that any of the programmable-gain arrays or volume controllers has completed slewing from a previous setting to a new programmed setting. If multiple gain arrays or volume controllers are changed at the same time, the SLD flag is set after the last volume slew completes. SLD also reports when the digital audio interface soft-start or soft-stop process has completed. MCLK is required for proper SLD operation. 0 = No volume slewing sequences have completed since the status register was last read. 1 = Volume slewing complete. Digital Audio Interface Unlocked 0 = Both digital audio interfaces are operating normally. 1 = Either digital audio interface is configured incorrectly or receiving invalid data. Jack Configuration Change JDET reports changes to any bit in the Jack Status register (0x02). Changes to the Jack Status bits are debounced before setting JDET. The debounce period is programmable using the JDEB bits. JDET is always set the first time JDETEN or SHDN is set the first time power is applied to the IC. Read the status register following such an event to clear JDET and allow for proper jack detection. 0 = No change in jack configuration. 1 = Jack configuration has changed. Full-Scale Interrupt Enable 0 = Disabled 1 = Enabled Volume Slew Complete Interrupt Enable 0 = Disabled 1 = Enabled Digital Audio Interface Unlocked Interrupt Enable 0 = Disabled 1 = Enabled Jack Configuration Change Interrupt Enable 0 = Disabled 1 = Enabled
6
SLD
0x00 (Read Only) 5 ULK
1
JDET
7
ICLD
6 0x0F 5
ISLD
IULK
1
IJDET
111
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Device Revision
Table 36. Device Revision Register
REGISTER BIT 7 6 5 0xFF (Read Only) 4 3 2 1 0 REV Device Revision Code REV is always set to 0x40. NAME DESCRIPTION
The IC features an I2C/SMBusK-compatible, 2-wire serial interface comprising a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the IC and the master at clock rates up to 400kHz. Figure 5 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the IC by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the IC is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the IC transmits the proper slave address followed by a series of nine SCL pulses. The IC transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or REPEATED START condition, a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500I, is required on SDA. SCL operates only as an input. A pullup resistor, typically greater than 500I, is required on SCL if there are multiple masters on the bus, or if the single master has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series
S SCL
I2C Serial Interface
resistors protect the digital inputs of the IC from high voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-tohigh transition on SDA while SCL is high (Figure 33). A START condition from the master signals the beginning of a transmission to the IC. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. Early STOP Conditions The IC recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition.
Sr P
SDA
Figure 33. START, STOP, and REPEATED START Conditions SMBus is a trademark of Intel Corp. 112
Stereo Audio Codec with FLEXSOUND Technology
Slave Address The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For the IC, the seven most significant bits are 0010000. Setting the read/write bit to 1 (slave address = 0x21) configures the IC for read mode. Setting the read/write bit to 0 (slave address = 0x20) configures the ICs for write mode. The address is the first byte of information sent to the IC after the START condition. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the IC uses to handshake receipt each byte of data when in write mode (Figure 34). The IC pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device
START CONDITION SCL 1 2
is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master retries communication. The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the IC is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the IC, followed by a STOP condition. Write Data Format A write to the IC includes transmission of a START condition, the slave address with the R/W bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition. Figure 35 illustrates the proper frame format for writing one byte of data to the IC. Figure 35 illustrates the frame format for writing n-bytes of data to the IC.
CLOCK PULSE FOR ACKNOWLEDGMENT
MAX98088
8 NOT ACKNOWLEDGE
9
SDA ACKNOWLEDGE
Figure 34. Acknowledge
ACKNOWLEDGE FROM MAX98088/ MAX98089 B7 ACKNOWLEDGE FROM MAX98088/ MAX98089 S SLAVE ADDRESS R/W O A ACKNOWLEDGE FROM MAX98088/ MAX98089 REGISTER ADDRESS A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P B6 B5 B4 B3 B2 B1 B0
Figure 35. Writing One Byte of Data to the ICs
ACKNOWLEDGE FROM MAX98088/ MAX98089 ACKNOWLEDGE FROM MAX98088/ MAX98089 S SLAVE ADDRESS R/W O A ACKNOWLEDGE FROM MAX98088/ MAX98089 REGISTER ADDRESS A B7 B6 B5 B4 B3 B2 B1 B0 DATA BYTE 1 1 BYTE A ACKNOWLEDGE FROM MAX98088/ MAX98089 B7 B6 B5 B4 B3 B2 B1 B0 DATA BYTE n 1 BYTE A P
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 36. Writing n-Bytes of Data to the ICs 113
Stereo Audio Codec with FLEXSOUND Technology MAX98088
The slave address with the R/W bit set to 0 indicates that the master intends to write data to the ICs. The ICs acknowledge receipt of the address byte during the master-generated 9th SCL pulse. The second byte transmitted from the master configures the IC's internal register address pointer. The pointer tells the IC where to write the next byte of data. An acknowledge pulse is sent by the ICs upon receipt of the address pointer data. The third byte sent to the ICs contains the data that is written to the chosen register. An acknowledge pulse from the ICs signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. The master signals the end of transmission by issuing a STOP condition. Register addresses greater than 0xC7 are reserved. Do not write to these addresses. Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The IC acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x00. The first byte transmitted from the ICs is the content of register 0x00. Transmitted data is valid on the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from register 0x00. The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the IC's slave address with the R/W bit set to 0 followed by the register address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The IC then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 37 illustrates the frame format for reading one byte from the IC. Figure 38 illustrates the frame format for reading multiple bytes from the ICs.
ACKNOWLEDGE FROM MAX98088/ MAX98089 S SLAVE ADDRESS R/W O A
ACKNOWLEDGE FROM MAX98088/ MAX98089 REGISTER ADDRESS A Sr
ACKNOWLEDGE FROM MAX98088/ MAX98089 SLAVE ADDRESS R/W 1 A
NOT ACKNOWLEDGE FROM MASTER DATA BYTE 1 BYTE A P
REPEATED START
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 37. Reading One Byte of Data from the ICs
ACKNOWLEDGE FROM MAX98088/ MAX98089 S SLAVE ADDRESS R/W O A
ACKNOWLEDGE FROM MAX98088/ MAX98089 REGISTER ADDRESS A Sr
ACKNOWLEDGE FROM MAX98088/ MAX98089 SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A
REPEATED START
Figure 38. Reading n Bytes of Data from the ICs 114
Stereo Audio Codec with FLEXSOUND Technology
Applications Information
Figures 39 and 40 provide example operating circuits for the ICs. sThe external components shown are the minimum required for the ICs to operate. Additional components may be required by the application.
2.8V TO 5.5V 1.8V 1.8V TO 3.6V 10FF
MAX98088
Typical Operating Circuits
1.8V TO 3.6V
1FF 1.8V TO 5.5V 10kI TO MICROCONTROLLER 10MHz TO 60MHz CLOCK INPUT IRQ MCLK BCLKS1 DIGITAL AUDIO PORT 1 LRCLKS1 SDINS1 SDOUTS1 I2C CONTROL PORT MICROPHONE OUTPUT TO BASEBAND SDA SCL MIC1P/DIGMICDATA MIC1N/DIGMICCLK MICBIAS 1FF MIC2P HEADSET MICROPHONE 1FF MIC2N 1FF HANDSET MICROPHONE INA1/EXTMICP 1FF INA2/EXTMICN 1FF 1kI LINE INPUT 1FF INB2 1FF INB1 DVDDS1 DVDD
1FF PVDD
1FF AVDD
1FF SPKLVDD
1FF SPKRVDD
1FF DVDDS2
1FF
BCLKS2 LRCLKS2 SDINS2 SDOUTS2 JACKSNS RECP/RXINP RECN/RXINN SPKLP JACKSNS BYPASS SWITCH INPUT DIGITAL AUDIO PORT 2
MAX98088
SPKLN SPKRP SPKRN
8I
8I
JACKSNS
1kI
2.2kI
HPR HPL HPSNS
REF
REG 1FF 2.2FF
DGND AGND HPGND SPKRGND SPKLGND HPVDD 1FF
HPVSS 1FF
C1N
C1P
1FF
Figure 39. Typical Application Circuit Using Analog Microphone Inputs and the Bypass Switch 115
Stereo Audio Codec with FLEXSOUND Technology MAX98088
2.8V TO 5.5V 1.8V 1.8V TO 3.6V 10FF
1.8V TO 3.6V
1FF 1.8V TO 5.5V 10kI TO MICROCONTROLLER 10MHz TO 60MHz CLOCK INPUT IRQ MCLK BCLKS1 DIGITAL AUDIO PORT 1 LRCLKS1 SDINS1 SDOUTS1 I2C CONTROL PORT SDA SCL MIC1P/DIGMICDATA MIC1N/DIGMICCLK MICBIAS 1FF MIC2P HEADSET MICROPHONE 1FF MIC2N 1FF INA1/EXTMICP LINE INPUT 1FF INA2/EXTMICN 1FF INB1 LINE INPUT 1FF INB2 1FF DVDDS1 DVDD
1FF PVDD
1FF AVDD
1FF SPKLVDD
1FF SPKRVDD
1FF DVDDS2
1FF
BCLKS2 LRCLKS2 SDINS2 SDOUTS2 JACKSNS RECP/RXINP RECN/RXINN SPKLP SPKLN JACKSNS DIGITAL AUDIO PORT 2
32I
DATA DIGITAL MIC 1 DIGITAL MIC 2 JACKSNS CLOCK DATA CLOCK
8I
MAX98088
SPKRP SPKRN HPR HPL HPSNS 8I
2.2kI
REF
REG 1FF 2.2FF
DGND AGND HPGND SPKRGND SPKLGND HPVDD 1FF
HPVSS 1FF
C1N
C1P
1FF
Figure 40. Typical Application Circuit Using the Digital Microphone Input and Receiver Amplifier 116
Stereo Audio Codec with FLEXSOUND Technology
Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier's output. The filters add cost, increase the solution size of the amplifier, and can decrease efficiency and THD+N performance. The traditional PWM scheme uses large differential output swings (2 x VDD peak to peak) and causes large ripple currents. Any parasitic resistance in the filter components results in a loss of power, lowering the efficiency. The IC does not require an output filter. The device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. Eliminating the output filter results in a smaller, less costly, more efficient solution. Because the frequency of the IC's output is well beyond the bandwidth of most speakers, voice coil movement due to the square-wave frequency is very small. Although this movement is small, a speaker not designed to handle the additional power can be damaged. For optimum results, use a speaker with a series inductance > 10FH. Typical 8I speakers exhibit series inductances in the 20FH to 100FH range. GSM radios transmit using time-division multiple access (TDMA) with 217Hz intervals. The result is an RF signal with strong amplitude modulation at 217Hz and its harmonics that is easily demodulated by audio amplifiers. The IC is designed specifically to reject RF signals; however, PCB layout has a large impact on the susceptibility of the end product.
Filterless Class D Operation
In RF applications, improvements to both layout and component selection decrease the IC's susceptibility to RF noise and prevent RF signals from being demodulated into audible noise. Trace lengths should be kept below 1/4 of the wavelength of the RF frequency of interest. Minimizing the trace lengths prevents them from functioning as antennas and coupling RF signals into the IC. The wavelength (l) in meters is given by: l = c/f where c = 3 x 108 m/s, and f = the RF frequency of interest. Route audio signals on middle layers of the PCB to allow ground planes above and below to shield them from RF interference. Ideally, the top and bottom layers of the PCB should primarily be ground planes to create effective shielding. Additional RF immunity can also be obtained by relying on the self-resonant frequency of capacitors as it exhibits a frequency response similar to a notch filter. Depending on the manufacturer, 10pF to 20pF capacitors typically exhibit self resonance at the RF frequencies of interest. These capacitors, when placed at the input pins, can effectively shunt the RF noise to ground. For these capacitors to be effective, they must have a lowimpedance, low-inductance path to the ground plane. Avoid using microvias to connect to the ground plane whenever possible as these vias do not conduct well at RF frequencies. To ensure proper device initialization and minimal clickand-pop, program the IC's SHDN = 1 after configuring all registers. Table 37 lists an example startup sequence for the device. To shut down the IC, simply set SHDN = 0.
MAX98088
RF Susceptibility
Startup/Shutdown Sequencing
Table 37. Example Startup Sequence
SEQUENCE 1 2 3 4 5 6 7 8 9 10 Ensure SHDN = 0 Configure clocks Configure digital audio interface Configure digital signal processing Load coefficients Configure mixers Configure gain and volume controls Configure miscellaneous functions Enable desired functions Set SHDN = 1 DESCRIPTION 0x51 0x10 to 0x13, 0x19 to 0x1B 0x14 to 0x17, 0x1C to 0x1F 0x18, 0x20, 0x3F to 0x46 0x52 to 0xC9 0x22 to 0x2D 0x2E to 0x3E 0x47 to 0x4B 0x4C, 0x50 0x51 REGISTERS
117
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Many configuration options in the ICs can be made while the devices are operating, however, some registers should only be adjusted when the corresponding audio path is disabled. Table 38 lists the registers that are sensitive during operation. Either disable the corresponding audio path or set SHDN = 0 while changing these registers. that removes the DC bias from an incoming analog signal. The AC coupling capacitor allows the amplifier to automatically bias the signal to an optimum DC level. Assuming zero-source impedance, the -3dB point of the highpass filter is given by: 1 f-3dB = 2RINCIN Choose CIN so that f-3dB is well below the lowest frequency of interest. For best audio quality use capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with highvoltage coefficients, such as ceramics, may result in increased distortion at low frequencies. Charge-Pump Capacitor Selection Use capacitors with an ESR less than 100mI for optimum performance. Low-ESR ceramic capacitors minimize the output resistance of the charge pump. Most surfacemount ceramic capacitors satisfy the ESR requirement. For best performance over the extended temperature range, select capacitors with an X7R dielectric.
Component Selection
Optional Ferrite Bead Filter In applications where speaker leads exceed 20mm, additional EMI suppression can be achieved by using a filter constructed from a ferrite bead and a capacitor to ground (Figure 41). Use a ferrite bead with low DC resistance, high-frequency (> 600MHz) impedance between 100I and 600I, and rated for at least 1A. The capacitor value varies based on the ferrite bead chosen and the actual speaker lead length. Select a capacitor less than 1nF based on EMI performance. Input Capacitor An input capacitor, CIN, in conjunction with the input impedance of the IC line inputs forms a highpass filter
Table 38. Registers That Are Sensitive to Changes During Operation
REGISTER 0x10 to 0x13, 0x19 to 0x1B 0x14 to 0x17, 0x1C to 0x1F 0x18, 0x20 0x25 to 0x2D 0x52 to 0xC9 DESCRIPTION Clock Control Registers Digital Audio Interface Configuration Digital Passband Filters Analog Mixers Digital Signal Processing Coefficients
SPK_P
MAX98088
SPK_N
Figure 41. Optional Class D Ferrite Bead Filter
118
Stereo Audio Codec with FLEXSOUND Technology
Charge-Pump Flying Capacitor The value of the flying capacitor (connected between C1N and C1P) affects the output resistance of the charge pump. A value that is too small degrades the device's ability to provide sufficient current drive, which leads to a loss of output voltage. Increasing the value of the flying capacitor reduces the charge-pump output resistance to an extent. Above 1FF, the on-resistance of the internal switches and the ESR of external chargepump capacitors dominate. Charge-Pump Holding Capacitor The holding capacitor (bypassing HPVSS) value and ESR directly affect the ripple at HPVSS. Increasing the capacitor's value reduces output ripple. Likewise, decreasing the ESR reduces both ripple and output resistance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics section for more information Table 39 shows how to connect the IC's pins when unused.
MAX98088
Unused Pins
Table 39. Unused Pins
NAME SPKRP SPKRVDD SPKLVDD SPKLP RECN/RXINN HPVDD C1P HPGND SPKRN SPKRGND SPKLGND SPKLN RECP/RXINP C1N HPL HPVSS SDINS1 LRCLKS1 HPSNS INB2 HPR DVDDS1 SDOUTS1 BCLKS1 JACKSNS CONNECTION Unconnected Always connected Always connect Unconnected Unconnected Unconnected Unconnected AGND Unconnected Always connect Always connect Unconnected Unconnected Unconnected Unconnected Unconnected AGND Unconnected AGND Unconnected Unconnected DVDD Unconnected Unconnected Unconnected NAME INB1 INA2/MICEXTN LRCLKS2 MCLK SDINS2 IRQ MIC1P/DIGMICDATA INA1/MICEXTP DGND BCLKS2 SDA SCL REG REF MIC1N/DIGMICCLK MIC2P SDOUTS2 DVDDS2 DVDD AVDD PVDD AGND MICBIAS MIC2N CONNECTION Unconnected Unconnected Unconnected Always connect AGND Unconnected Unconnected Unconnected Always connect Unconnected Always connect Always connect Always connect Always connect Unconnected Unconnected Unconnected DVDD Always connect Always connect Always connect Always connect Unconnected Unconnected
119
Stereo Audio Codec with FLEXSOUND Technology MAX98088
The IC uses a 63-bump WLP package. Figure 42 provides an example of how to connect to all active bumps using 3 layers of the PCB. To ensure uninterrupted ground returns, use layer 2 as a connecting layer between layer 1 and layer 2 and flood the remaining area with ground.
Recommended PCB Routing
Proper layout and grounding are essential for optimum performance. When designing a PCB for the ICs, partition the circuitry so that the analog sections of the IC are separated from the digital sections. This ensures that the analog audio traces are not routed near digital traces. Use a large continuous ground plane on a dedicated layer of the PCB to minimize loop areas. Connect AGND, DGND, HPGND, SPKLGND, and SPKRGND directly to the ground plane using the shortest trace length possible. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any digital noise from coupling into the analog audio signals. Ground the bypass capacitors on MICBIAS, REG, PREG, and REF directly to the ground plane with minimum trace length. Also be sure to minimize the path length to AGND. Bypass AVDD directly to AGND. Connect all digital I/O termination to the ground plane with minimum path length to DGND. Bypass DVDD, DVDDS1, and DVDDS2 directly to DGND. Place the capacitor between C1P and C1N as close as possible to the ICs to minimize trace length from C1P to C1N. Inductance and resistance added between C1P and C1N reduce the output power of the headphone amplifier. Bypass HPVSS with a capacitor located close to HPVSS with a short trace length to HPGND. Close decoupling of HPVSS minimizes supply ripple and maximizes output power from the headphone amplifier.
Supply Bypassing, Layout, and Grounding
LAYER 1
LAYER 2
HPSNS senses ground noise on the headphone jack and adds the same noise to the output audio signal, thereby making the output (headphone output minus ground) noise free. Connect HPSNS to the headphone jack shield to ensure accurate pickup of headphone ground noise. Bypass SPKLVDD and SPKRVDD to SPKLGND and SPKRGND, respectively, with as little trace length as possible. Connect SPKLP, SPKLN, SPKRP, and SPKRN to the stereo speakers using the shortest traces possible. Reducing trace length minimizes radiated EMI. Route SPKLP/SPKLN and SPKRP/SPKRN as differential pairs on the PCB to minimize loop area, thereby the inductance of the circuit. If filter components are used on the speaker outputs, be sure to locate them as close as possible to the IC to ensure maximum effectiveness. Minimize the trace length from any ground-connected passive components to SPKLGND and SPKRGND to further minimize radiated EMI.
LAYER 3
Figure 42. Suggested Routing for the MAX98088
120
Stereo Audio Codec with FLEXSOUND Technology
Route microphone signals from the microphone to the ICs as a differential pair, ensuring that the positive and negative signals follow the same path as closely as possible with equal trace length. When using single-ended microphones or other single-ended audio sources, ground the negative microphone input as close as possible to the audio source and then treat the positive and negative traces as differential pairs. An evaluation kit (EV kit) is available to provide an example layout for the IC. The EV kit allows quick setup of the IC and includes easy-to-use software allowing all internal registers to be controlled. For the latest application details on WLP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note 1891: WaferLevel Packaging (WLP) and Its Applications. Figure 43 shows the dimensions of the WLP balls used on the MAX98088.
MAX98088
0.24mm
WLP Applications Information
0.21mm
Figure 43. WLP Ball Dimensions
121
Stereo Audio Codec with FLEXSOUND Technology MAX98088
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 63 WLP PACKAGE CODE W633A3+1 OUTLINE NO. 21-0462 LAND PATTERN NO. --
122
Stereo Audio Codec with FLEXSOUND Technology
Revision History
REVISION NUMBER 0 REVISION DATE 6/10 Initial release DESCRIPTION PAGES CHANGED --
MAX98088
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c)
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2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.

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Price & Availability of MAX98088

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